Clement Le Marquis | 6abb36e | 2021-03-25 17:30:32 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2018 NXP |
| 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * Boot command to get and set the PRIBLOB bitfield form the SCFGR register |
| 8 | * of the CAAM IP. It is recommended to set this bitfield to 3 once your |
| 9 | * encrypted boot image is ready, to prevent the generation of blobs usable |
| 10 | * to decrypt an encrypted boot image. |
| 11 | */ |
| 12 | |
| 13 | #include <asm/io.h> |
Clement Le Marquis | 6abb36e | 2021-03-25 17:30:32 +0800 | [diff] [blame] | 14 | #include <command.h> |
Maximus Sun | 199d193 | 2023-06-15 18:09:26 +0800 | [diff] [blame] | 15 | #include <fsl_sec.h> |
Clement Le Marquis | 6abb36e | 2021-03-25 17:30:32 +0800 | [diff] [blame] | 16 | |
Peng Fan | 44d77a3 | 2021-08-07 16:21:34 +0800 | [diff] [blame] | 17 | int do_priblob_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) |
Clement Le Marquis | 6abb36e | 2021-03-25 17:30:32 +0800 | [diff] [blame] | 18 | { |
Maximus Sun | 199d193 | 2023-06-15 18:09:26 +0800 | [diff] [blame] | 19 | ccsr_sec_t *sec_regs = (ccsr_sec_t *)CAAM_BASE_ADDR; |
| 20 | u32 scfgr = sec_in32(&sec_regs->scfgr); |
| 21 | |
| 22 | scfgr |= 0x3; |
| 23 | sec_out32(&sec_regs->scfgr, scfgr); |
| 24 | printf("New priblob setting = 0x%x\n", sec_in32(&sec_regs->scfgr) & 0x3); |
Clement Le Marquis | 6abb36e | 2021-03-25 17:30:32 +0800 | [diff] [blame] | 25 | |
| 26 | return 0; |
| 27 | } |
| 28 | |
| 29 | U_BOOT_CMD( |
| 30 | set_priblob_bitfield, 1, 0, do_priblob_write, |
| 31 | "Set the PRIBLOB bitfield to 3", |
| 32 | "<value>\n" |
| 33 | " - Write 3 in PRIBLOB bitfield of SCFGR regiter of CAAM IP.\n" |
| 34 | " Prevent the generation of blobs usable to decrypt an\n" |
| 35 | " encrypted boot image." |
| 36 | ); |