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Dirk Behmebab104e2009-01-28 21:40:16 +01001/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
7 *
8 * Configuration settings for the TI OMAP3430 Zoom MDK board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31#include <asm/sizes.h>
32
33/*
34 * High Level Configuration Options
35 */
36#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
37#define CONFIG_OMAP 1 /* in a TI OMAP core */
38#define CONFIG_OMAP34XX 1 /* which is a 34XX */
39#define CONFIG_OMAP3430 1 /* which is in a 3430 */
40#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
41
42#include <asm/arch/cpu.h> /* get chip and board defs */
43#include <asm/arch/omap3.h>
44
Sanjeev Premie32ef2e2009-04-27 21:27:27 +053045/*
46 * Display CPU and Board information
47 */
48#define CONFIG_DISPLAY_CPUINFO 1
49#define CONFIG_DISPLAY_BOARDINFO 1
50
Dirk Behmebab104e2009-01-28 21:40:16 +010051/* Clock Defines */
52#define V_OSCK 26000000 /* Clock output from T2 */
53#define V_SCLK (V_OSCK >> 1)
54
55#undef CONFIG_USE_IRQ /* no support for IRQs */
56#define CONFIG_MISC_INIT_R
57
58#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
59#define CONFIG_SETUP_MEMORY_TAGS 1
60#define CONFIG_INITRD_TAG 1
61#define CONFIG_REVISION_TAG 1
62
63/*
64 * Size of malloc() pool
65 */
66#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
67 /* Sector */
68#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
69#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
70 /* initial data */
71
72/*
73 * Hardware drivers
74 */
75
76/*
77 * NS16550 Configuration
78 */
79#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
80
81#define CONFIG_SYS_NS16550
82#define CONFIG_SYS_NS16550_SERIAL
83#define CONFIG_SYS_NS16550_REG_SIZE (-4)
84#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
85
86/*
87 * select serial console configuration
88 */
89#define CONFIG_CONS_INDEX 3
90#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
91#define CONFIG_SERIAL3 3 /* UART3 */
92
93/* allow to overwrite serial and ethaddr */
94#define CONFIG_ENV_OVERWRITE
95#define CONFIG_BAUDRATE 115200
96#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
97 115200}
98#define CONFIG_MMC 1
99#define CONFIG_OMAP3_MMC 1
100#define CONFIG_DOS_PARTITION 1
101
102/* commands to include */
103#include <config_cmd_default.h>
104
105#define CONFIG_CMD_EXT2 /* EXT2 Support */
106#define CONFIG_CMD_FAT /* FAT support */
107#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
108
109#define CONFIG_CMD_I2C /* I2C serial bus support */
110#define CONFIG_CMD_MMC /* MMC support */
111#define CONFIG_CMD_NAND /* NAND support */
Nishanth Menoneb7b1882009-02-02 18:20:12 -0600112#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
Dirk Behmebab104e2009-01-28 21:40:16 +0100113
114#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
115#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
116#undef CONFIG_CMD_IMI /* iminfo */
117#undef CONFIG_CMD_IMLS /* List all found images */
118#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
119#undef CONFIG_CMD_NFS /* NFS support */
120
121#define CONFIG_SYS_NO_FLASH
122#define CONFIG_SYS_I2C_SPEED 100000
123#define CONFIG_SYS_I2C_SLAVE 1
124#define CONFIG_SYS_I2C_BUS 0
125#define CONFIG_SYS_I2C_BUS_SELECT 1
126#define CONFIG_DRIVER_OMAP34XX_I2C 1
127
128/*
129 * Board NAND Info.
130 */
131#define CONFIG_NAND_OMAP_GPMC
132#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
133 /* to access nand */
134#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
135 /* to access nand at */
136 /* CS0 */
137#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
138
139#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
140 /* devices */
Dirk Behmebab104e2009-01-28 21:40:16 +0100141#define CONFIG_JFFS2_NAND
142/* nand device jffs2 lives on */
143#define CONFIG_JFFS2_DEV "nand0"
144/* start of jffs2 partition */
145#define CONFIG_JFFS2_PART_OFFSET 0x680000
146#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
147 /* partition */
148
149/* Environment information */
150#define CONFIG_BOOTDELAY 10
151
152#define CONFIG_EXTRA_ENV_SETTINGS \
153 "loadaddr=0x82000000\0" \
154 "console=ttyS2,115200n8\0" \
155 "videomode=1024x768@60,vxres=1024,vyres=768\0" \
156 "videospec=omapfb:vram:2M,vram:4M\0" \
157 "mmcargs=setenv bootargs console=${console} " \
158 "video=${videospec},mode:${videomode} " \
159 "root=/dev/mmcblk0p2 rw " \
160 "rootfstype=ext3 rootwait\0" \
161 "nandargs=setenv bootargs console=${console} " \
162 "video=${videospec},mode:${videomode} " \
163 "root=/dev/mtdblock4 rw " \
164 "rootfstype=jffs2\0" \
165 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
166 "bootscript=echo Running bootscript from mmc ...; " \
Wolfgang Denk85c25df2009-04-01 23:34:12 +0200167 "source ${loadaddr}\0" \
Dirk Behmebab104e2009-01-28 21:40:16 +0100168 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
169 "mmcboot=echo Booting from mmc ...; " \
170 "run mmcargs; " \
171 "bootm ${loadaddr}\0" \
172 "nandboot=echo Booting from nand ...; " \
173 "run nandargs; " \
174 "nand read ${loadaddr} 280000 400000; " \
175 "bootm ${loadaddr}\0" \
176
177#define CONFIG_BOOTCOMMAND \
Dirk Behmed4159f12009-04-21 17:30:51 +0200178 "if mmc init; then " \
Dirk Behmebab104e2009-01-28 21:40:16 +0100179 "if run loadbootscript; then " \
180 "run bootscript; " \
181 "else " \
182 "if run loaduimage; then " \
183 "run mmcboot; " \
184 "else run nandboot; " \
185 "fi; " \
186 "fi; " \
187 "else run nandboot; fi"
188
189#define CONFIG_AUTO_COMPLETE 1
190/*
191 * Miscellaneous configurable options
192 */
193#define V_PROMPT "OMAP3 Zoom1# "
194
195#define CONFIG_SYS_LONGHELP /* undef to save memory */
196#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
197#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
198#define CONFIG_SYS_PROMPT V_PROMPT
199#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
200/* Print Buffer Size */
201#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
202 sizeof(CONFIG_SYS_PROMPT) + 16)
203#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
204/* Boot Argument Buffer Size */
205#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
206
207#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
208 /* works on */
209#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
210 0x01F00000) /* 31MB */
211
Dirk Behmebab104e2009-01-28 21:40:16 +0100212#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
213 /* load address */
214
215/*
Manikandan Pillaie8b16962009-04-21 17:29:05 +0200216 * OMAP3 has 12 GP timers, they can be driven by the system clock
217 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
218 * This rate is divided by a local divisor.
Dirk Behmebab104e2009-01-28 21:40:16 +0100219 */
Manikandan Pillaie8b16962009-04-21 17:29:05 +0200220#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
221#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
222#define CONFIG_SYS_HZ 1000
Dirk Behmebab104e2009-01-28 21:40:16 +0100223
224/*-----------------------------------------------------------------------
225 * Stack sizes
226 *
227 * The stack sizes are set up in start.S using the settings below
228 */
229#define CONFIG_STACKSIZE SZ_128K /* regular stack */
230#ifdef CONFIG_USE_IRQ
231#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
232#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
233#endif
234
235/*-----------------------------------------------------------------------
236 * Physical Memory Map
237 */
238#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
239#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
240#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
241#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
242
243/* SDRAM Bank Allocation method */
244#define SDRC_R_B_C 1
245
246/*-----------------------------------------------------------------------
247 * FLASH and environment organization
248 */
249
250/* **** PISMO SUPPORT *** */
251
252/* Configure the PISMO */
253#define PISMO1_NAND_SIZE GPMC_SIZE_128M
254#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
255
256#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
257 /* one chip */
258#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
259#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
260
261#define CONFIG_SYS_FLASH_BASE boot_flash_base
262
263/* Monitor at start of flash */
264#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
265#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
266
267#define CONFIG_ENV_IS_IN_NAND 1
268#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
269#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
270
271#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
272#define CONFIG_ENV_OFFSET boot_flash_off
273#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
274
275/*-----------------------------------------------------------------------
276 * CFI FLASH driver setup
277 */
278/* timeout values are in ticks */
279#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
280#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
281
282/* Flash banks JFFS2 should use */
283#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
284 CONFIG_SYS_MAX_NAND_DEVICE)
285#define CONFIG_SYS_JFFS2_MEM_NAND
286/* use flash_info[2] */
287#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
288#define CONFIG_SYS_JFFS2_NUM_BANKS 1
289
290#ifndef __ASSEMBLY__
291extern gpmc_csx_t *nand_cs_base;
292extern gpmc_t *gpmc_cfg_base;
293extern unsigned int boot_flash_base;
294extern volatile unsigned int boot_flash_env_addr;
295extern unsigned int boot_flash_off;
296extern unsigned int boot_flash_sec;
297extern unsigned int boot_flash_type;
298#endif
299
Dirk Behmebab104e2009-01-28 21:40:16 +0100300#endif /* __CONFIG_H */