blob: 300be8b093faab319914da99e2e51045766f0d12 [file] [log] [blame]
Simon Glass466c7852019-12-06 21:42:18 -07001// SPDX-License-Identifier: Intel
2/*
3 * Copyright (C) 2015-2016 Intel Corp.
4 * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
5 * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
6 * Mostly taken from coreboot fsp2_0/memory_init.c
7 */
8
9#include <common.h>
10#include <binman.h>
11#include <asm/mrccache.h>
12#include <asm/fsp/fsp_infoheader.h>
13#include <asm/fsp2/fsp_api.h>
14#include <asm/fsp2/fsp_internal.h>
15#include <asm/arch/fsp/fsp_configs.h>
16#include <asm/arch/fsp/fsp_m_upd.h>
17
18static int prepare_mrc_cache_type(enum mrc_type_t type,
19 struct mrc_data_container **cachep)
20{
21 struct mrc_data_container *cache;
22 struct mrc_region entry;
23 int ret;
24
25 ret = mrccache_get_region(type, NULL, &entry);
26 if (ret)
27 return ret;
28 cache = mrccache_find_current(&entry);
29 if (!cache)
30 return -ENOENT;
31
32 log_debug("MRC at %x, size %x\n", (uint)cache->data, cache->data_size);
33 *cachep = cache;
34
35 return 0;
36}
37
38int prepare_mrc_cache(struct fspm_upd *upd)
39{
40 struct mrc_data_container *cache;
41 int ret;
42
43 ret = prepare_mrc_cache_type(MRC_TYPE_NORMAL, &cache);
44 if (ret)
45 return log_msg_ret("Cannot get normal cache", ret);
46 upd->arch.nvs_buffer_ptr = cache->data;
47
48 ret = prepare_mrc_cache_type(MRC_TYPE_VAR, &cache);
49 if (ret)
50 return log_msg_ret("Cannot get var cache", ret);
51 upd->config.variable_nvs_buffer_ptr = cache->data;
52
53 return 0;
54}
55
56int fsp_memory_init(bool s3wake, bool use_spi_flash)
57{
58 struct fspm_upd upd, *fsp_upd;
59 fsp_memory_init_func func;
60 struct binman_entry entry;
61 struct fsp_header *hdr;
62 struct hob_header *hob;
63 struct udevice *dev;
64 int ret;
65
66 ret = fsp_locate_fsp(FSP_M, &entry, use_spi_flash, &dev, &hdr, NULL);
67 if (ret)
68 return log_msg_ret("locate FSP", ret);
69 debug("Found FSP_M at %x, size %x\n", hdr->img_base, hdr->img_size);
70
71 /* Copy over the default config */
72 fsp_upd = (struct fspm_upd *)(hdr->img_base + hdr->cfg_region_off);
73 if (fsp_upd->header.signature != FSPM_UPD_SIGNATURE)
74 return log_msg_ret("Bad UPD signature", -EPERM);
75 memcpy(&upd, fsp_upd, sizeof(upd));
76
77 ret = fspm_update_config(dev, &upd);
78 if (ret)
79 return log_msg_ret("Could not setup config", ret);
80
81 debug("SDRAM init...");
Simon Glassea6a6092020-05-10 11:39:59 -060082 bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_M, "fsp-m");
Simon Glass466c7852019-12-06 21:42:18 -070083 func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init);
84 ret = func(&upd, &hob);
Simon Glassea6a6092020-05-10 11:39:59 -060085 bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_M);
Simon Glass466c7852019-12-06 21:42:18 -070086 if (ret)
87 return log_msg_ret("SDRAM init fail\n", ret);
88
89 gd->arch.hob_list = hob;
90 debug("done\n");
91
92 ret = fspm_done(dev);
93 if (ret)
94 return log_msg_ret("fsm_done\n", ret);
95
96 return 0;
97}