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git01.mediatek.com / filogic / uboot / 1e81b3092792206f868167dfa27b407acfc7bfe2 / . / arch / arm / include / asm / arch-am33xx / mux_am43xx.h
blob: 256c5e243f8be2f1cbec28ed957eead57fa0df8a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]2/*
3 * mux_am43xx.h
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]6 */
7
8#ifndef _MUX_AM43XX_H_
9#define _MUX_AM43XX_H_
10
11#include <common.h>
12#include <asm/io.h>
13
14#define MUX_CFG(value, offset) \
15 __raw_writel(value, (CTRL_BASE + offset));
16
17/* PAD Control Fields */
18#define SLEWCTRL (0x1 << 19)
19#define RXACTIVE (0x1 << 18)
20#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */
21#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */
22#define PULLUDEN (0x0 << 16) /* Pull up/down enable */
23#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */
24#define MODE(val) val /* used for Readability */
25
26/*
27 * PAD CONTROL OFFSETS
28 * Field names corresponds to the pad signal name
29 */
30struct pad_signals {
31 int gpmc_ad0;
32 int gpmc_ad1;
33 int gpmc_ad2;
34 int gpmc_ad3;
35 int gpmc_ad4;
36 int gpmc_ad5;
37 int gpmc_ad6;
38 int gpmc_ad7;
39 int gpmc_ad8;
40 int gpmc_ad9;
41 int gpmc_ad10;
42 int gpmc_ad11;
43 int gpmc_ad12;
44 int gpmc_ad13;
45 int gpmc_ad14;
46 int gpmc_ad15;
47 int gpmc_a0;
48 int gpmc_a1;
49 int gpmc_a2;
50 int gpmc_a3;
51 int gpmc_a4;
52 int gpmc_a5;
53 int gpmc_a6;
54 int gpmc_a7;
55 int gpmc_a8;
56 int gpmc_a9;
57 int gpmc_a10;
58 int gpmc_a11;
59 int gpmc_wait0;
60 int gpmc_wpn;
61 int gpmc_be1n;
62 int gpmc_csn0;
63 int gpmc_csn1;
64 int gpmc_csn2;
65 int gpmc_csn3;
66 int gpmc_clk;
67 int gpmc_advn_ale;
68 int gpmc_oen_ren;
69 int gpmc_wen;
70 int gpmc_be0n_cle;
71 int lcd_data0;
72 int lcd_data1;
73 int lcd_data2;
74 int lcd_data3;
75 int lcd_data4;
76 int lcd_data5;
77 int lcd_data6;
78 int lcd_data7;
79 int lcd_data8;
80 int lcd_data9;
81 int lcd_data10;
82 int lcd_data11;
83 int lcd_data12;
84 int lcd_data13;
85 int lcd_data14;
86 int lcd_data15;
87 int lcd_vsync;
88 int lcd_hsync;
89 int lcd_pclk;
90 int lcd_ac_bias_en;
91 int mmc0_dat3;
92 int mmc0_dat2;
93 int mmc0_dat1;
94 int mmc0_dat0;
95 int mmc0_clk;
96 int mmc0_cmd;
97 int mii1_col;
98 int mii1_crs;
99 int mii1_rxerr;
100 int mii1_txen;
101 int mii1_rxdv;
102 int mii1_txd3;
103 int mii1_txd2;
104 int mii1_txd1;
105 int mii1_txd0;
106 int mii1_txclk;
107 int mii1_rxclk;
108 int mii1_rxd3;
109 int mii1_rxd2;
110 int mii1_rxd1;
111 int mii1_rxd0;
112 int rmii1_refclk;
113 int mdio_data;
114 int mdio_clk;
115 int spi0_sclk;
116 int spi0_d0;
117 int spi0_d1;
118 int spi0_cs0;
119 int spi0_cs1;
120 int ecap0_in_pwm0_out;
121 int uart0_ctsn;
122 int uart0_rtsn;
123 int uart0_rxd;
124 int uart0_txd;
125 int uart1_ctsn;
126 int uart1_rtsn;
127 int uart1_rxd;
128 int uart1_txd;
129 int i2c0_sda;
130 int i2c0_scl;
131 int mcasp0_aclkx;
132 int mcasp0_fsx;
133 int mcasp0_axr0;
134 int mcasp0_ahclkr;
135 int mcasp0_aclkr;
136 int mcasp0_fsr;
137 int mcasp0_axr1;
138 int mcasp0_ahclkx;
Bryan De Faria7c2b52d2015-04-02 10:57:07 +0200[diff] [blame]139 int cam0_hd;
140 int cam0_vd;
141 int cam0_field;
142 int cam0_wen;
143 int cam0_pclk;
144 int cam0_data8;
145 int cam0_data9;
146 int cam1_data9;
147 int cam1_data8;
148 int cam1_hd;
149 int cam1_vd;
150 int cam1_pclk;
151 int cam1_field;
152 int cam1_wen;
153 int cam1_data0;
154 int cam1_data1;
155 int cam1_data2;
156 int cam1_data3;
157 int cam1_data4;
158 int cam1_data5;
159 int cam1_data6;
160 int cam1_data7;
161 int cam0_data0;
162 int cam0_data1;
163 int cam0_data2;
164 int cam0_data3;
165 int cam0_data4;
166 int cam0_data5;
167 int cam0_data6;
168 int cam0_data7;
169 int uart3_rxd;
170 int uart3_txd;
171 int uart3_ctsn;
172 int uart3_rtsn;
173 int gpio5_8;
174 int gpio5_9;
175 int gpio5_10;
176 int gpio5_11;
177 int gpio5_12;
178 int gpio5_13;
179 int spi4_sclk;
180 int spi4_d0;
181 int spi4_d1;
182 int spi4_cs0;
183 int spi2_sclk;
184 int spi2_d0;
185 int spi2_d1;
186 int spi2_cs0;
187 int xdma_evt_intr0;
188 int xdma_evt_intr1;
189 int clkreq;
Lokesh Vutlae6bd05e2013-12-10 15:02:19 +0530[diff] [blame]190 int nresetin_out;
Lokesh Vutlae6bd05e2013-12-10 15:02:19 +0530[diff] [blame]191 int rsvd1;
Bryan De Faria7c2b52d2015-04-02 10:57:07 +0200[diff] [blame]192 int nnmi;
193 int rsvd2;
194 int rsvd3;
Lokesh Vutlae6bd05e2013-12-10 15:02:19 +0530[diff] [blame]195 int tms;
196 int tdi;
197 int tdo;
198 int tck;
199 int ntrst;
200 int emu0;
201 int emu1;
202 int osc1_in;
203 int osc1_out;
Lokesh Vutlae6bd05e2013-12-10 15:02:19 +0530[diff] [blame]204 int rtc_porz;
Bryan De Faria7c2b52d2015-04-02 10:57:07 +0200[diff] [blame]205 int ext_wakeup0;
206 int pmic_power_en0;
Lokesh Vutlae6bd05e2013-12-10 15:02:19 +0530[diff] [blame]207 int usb0_drvvbus;
Lokesh Vutlae6bd05e2013-12-10 15:02:19 +0530[diff] [blame]208 int usb1_drvvbus;
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]209};
210
211#endif /* _MUX_AM43XX_H_ */