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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simekeb1dfa72013-02-04 12:38:59 +01002/*
3 * Copyright (c) 2013 Xilinx Inc.
Michal Simekeb1dfa72013-02-04 12:38:59 +01004 */
5
6#ifndef _SYS_PROTO_H_
7#define _SYS_PROTO_H_
8
9extern void zynq_slcr_lock(void);
10extern void zynq_slcr_unlock(void);
11extern void zynq_slcr_cpu_reset(void);
Michal Simek15d654c2013-04-22 15:43:02 +020012extern void zynq_slcr_devcfg_disable(void);
13extern void zynq_slcr_devcfg_enable(void);
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053014extern u32 zynq_slcr_get_boot_mode(void);
Michal Simek15d654c2013-04-22 15:43:02 +020015extern u32 zynq_slcr_get_idcode(void);
Michal Simek8d191622014-04-25 12:21:04 +020016extern int zynq_slcr_get_mio_pin_status(const char *periph);
Michal Simekf5ff7bc2013-06-17 14:37:01 +020017extern void zynq_ddrc_init(void);
Siva Durga Prasad Paladugue26ef3b2013-11-29 19:01:25 +053018extern unsigned int zynq_get_silicon_version(void);
Michal Simekeb1dfa72013-02-04 12:38:59 +010019
Joe Hershberger7f4e5552016-01-26 11:57:03 -060020int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
21
Michal Simekeb1dfa72013-02-04 12:38:59 +010022#endif /* _SYS_PROTO_H_ */