blob: 03e9364765d06c75aa20bcc021b46de3d5241dbb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefano Babic4c8d4122016-06-06 11:19:42 +02002/*
3 * Copyright (C) Stefano Babic <sbabic@denx.de>
4 *
5 * Based on other i.MX6 boards
Stefano Babic4c8d4122016-06-06 11:19:42 +02006 */
7
Simon Glass1e268642020-05-10 11:39:55 -06008#include <common.h>
Simon Glassa7b51302019-11-14 12:57:46 -07009#include <init.h>
Stefano Babic4c8d4122016-06-06 11:19:42 +020010#include <asm/arch/clock.h>
11#include <asm/arch/imx-regs.h>
12#include <asm/arch/iomux.h>
13#include <asm/arch/mx6-pins.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060014#include <env.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090015#include <linux/errno.h>
Stefano Babic4c8d4122016-06-06 11:19:42 +020016#include <asm/gpio.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020017#include <asm/mach-imx/mxc_i2c.h>
18#include <asm/mach-imx/iomux-v3.h>
19#include <asm/mach-imx/boot_mode.h>
20#include <asm/mach-imx/video.h>
Stefano Babic4c8d4122016-06-06 11:19:42 +020021#include <mmc.h>
Yangbo Lu73340382019-06-21 11:42:28 +080022#include <fsl_esdhc_imx.h>
Stefano Babic4c8d4122016-06-06 11:19:42 +020023#include <miiphy.h>
24#include <netdev.h>
25#include <asm/arch/mxc_hdmi.h>
26#include <asm/arch/crm_regs.h>
27#include <asm/io.h>
28#include <asm/arch/sys_proto.h>
29#include <i2c.h>
Diego Dorta2661c9c2017-09-22 12:12:18 -030030#include <input.h>
Stefano Babic4c8d4122016-06-06 11:19:42 +020031#include <power/pmic.h>
32#include <power/pfuze100_pmic.h>
33#include <asm/arch/mx6-ddr.h>
34
35DECLARE_GLOBAL_DATA_PTR;
36
37#define OPEN_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_DISABLE | (0 << 12))
38
39#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
44 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
45 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46
47#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
49
50#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
52
53#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
55
56#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
57 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
58
59#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
61 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
62
63#define I2C_PMIC 1
64
65#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
66
67#define ETH_PHY_RESET IMX_GPIO_NR(2, 4)
68
69int dram_init(void)
70{
71 gd->ram_size = imx_ddr_size();
72
73 return 0;
74}
75
76iomux_v3_cfg_t const uart2_pads[] = {
77 MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
78 MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
79};
80
81static void setup_iomux_uart(void)
82{
83 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
84}
85
86#ifdef CONFIG_TARGET_ZC5202
87iomux_v3_cfg_t const enet_pads[] = {
88 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
95 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
102 /* Switch Reset */
103 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
104 /* Switch Interrupt */
105 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
106 /* use CRS and COL pads as GPIOs */
107 MX6_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(OPEN_PAD_CTRL),
108 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(OPEN_PAD_CTRL),
109
110};
111
112#define BOARD_NAME "EL6x-ZC5202"
113#else
114iomux_v3_cfg_t const enet_pads[] = {
115 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
124 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
126 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
127 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
128 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
129 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
130 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
131 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
132};
133#define BOARD_NAME "EL6x-ZC5601"
134#endif
135
136static void setup_iomux_enet(void)
137{
138 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
139
140#ifdef CONFIG_TARGET_ZC5202
141 /* set CRS and COL to input */
142 gpio_direction_input(IMX_GPIO_NR(4, 9));
143 gpio_direction_input(IMX_GPIO_NR(4, 12));
144
145 /* Reset Switch */
146 gpio_direction_output(ETH_PHY_RESET , 0);
147 mdelay(2);
148 gpio_set_value(ETH_PHY_RESET, 1);
149#endif
150}
151
152int board_phy_config(struct phy_device *phydev)
153{
154 if (phydev->drv->config)
155 phydev->drv->config(phydev);
156
157 return 0;
158}
159
160#ifdef CONFIG_MXC_SPI
161#ifdef CONFIG_TARGET_ZC5202
162iomux_v3_cfg_t const ecspi1_pads[] = {
163 MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
164 MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
165 MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
166 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
167 MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
168};
169
170iomux_v3_cfg_t const ecspi3_pads[] = {
171 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
172 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
173 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
174 MX6_PAD_DISP0_DAT7__GPIO4_IO28 | MUX_PAD_CTRL(SPI_PAD_CTRL),
175 MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(SPI_PAD_CTRL),
176 MX6_PAD_DISP0_DAT9__GPIO4_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL),
177 MX6_PAD_DISP0_DAT10__GPIO4_IO31 | MUX_PAD_CTRL(SPI_PAD_CTRL),
178};
179#endif
180
181iomux_v3_cfg_t const ecspi4_pads[] = {
182 MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
183 MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
184 MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
185 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
186};
187
188int board_spi_cs_gpio(unsigned bus, unsigned cs)
189{
190 return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
191 ? (IMX_GPIO_NR(3, 20)) : -1;
192}
193
194static void setup_spi(void)
195{
196#ifdef CONFIG_TARGET_ZC5202
197 gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
198 gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
199 gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
200 gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
201 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
202#endif
203
204 gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
205 gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
206 imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
207
208 enable_spi_clk(true, 3);
209}
210#endif
211
212static struct i2c_pads_info i2c_pad_info1 = {
213 .scl = {
214 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD,
215 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD,
216 .gp = IMX_GPIO_NR(2, 30)
217 },
218 .sda = {
219 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
220 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
221 .gp = IMX_GPIO_NR(4, 13)
222 }
223};
224
225static struct i2c_pads_info i2c_pad_info2 = {
226 .scl = {
227 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
228 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
229 .gp = IMX_GPIO_NR(1, 5)
230 },
231 .sda = {
232 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD,
233 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD,
234 .gp = IMX_GPIO_NR(7, 11)
235 }
236};
237
238iomux_v3_cfg_t const usdhc2_pads[] = {
239 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
240 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
241 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
242 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
243 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
244 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
245 MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
246};
247
248iomux_v3_cfg_t const usdhc4_pads[] = {
249 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
250 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
251 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
252 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
253 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
254 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
255 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
256 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
258 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
259};
260
Yangbo Lu73340382019-06-21 11:42:28 +0800261#ifdef CONFIG_FSL_ESDHC_IMX
Stefano Babic4c8d4122016-06-06 11:19:42 +0200262struct fsl_esdhc_cfg usdhc_cfg[2] = {
263 {USDHC2_BASE_ADDR},
264 {USDHC4_BASE_ADDR},
265};
266
267#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
268
269int board_mmc_getcd(struct mmc *mmc)
270{
271 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
272 int ret = 0;
273
274 switch (cfg->esdhc_base) {
275 case USDHC2_BASE_ADDR:
276 ret = !gpio_get_value(USDHC2_CD_GPIO);
277 break;
278 case USDHC4_BASE_ADDR:
279 ret = 1; /* eMMC/uSDHC4 is always present */
280 break;
281 }
282
283 return ret;
284}
285
286int board_mmc_init(bd_t *bis)
287{
288#ifndef CONFIG_SPL_BUILD
289 int ret;
290 int i;
291
292 /*
293 * According to the board_mmc_init() the following map is done:
294 * (U-boot device node) (Physical Port)
295 * mmc0 SD2
296 * mmc1 SD3
297 * mmc2 eMMC
298 */
299 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
300 switch (i) {
301 case 0:
302 imx_iomux_v3_setup_multiple_pads(
303 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
304 gpio_direction_input(USDHC2_CD_GPIO);
305 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
306 break;
307 case 1:
308 imx_iomux_v3_setup_multiple_pads(
309 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
310 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
311 break;
312 default:
313 printf("Warning: you configured more USDHC controllers"
314 "(%d) then supported by the board (%d)\n",
315 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
316 return -EINVAL;
317 }
318
319 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
320 if (ret)
321 return ret;
322 }
323
324 return 0;
325#else
326 struct src *psrc = (struct src *)SRC_BASE_ADDR;
327 unsigned reg = readl(&psrc->sbmr1) >> 11;
328
329 /*
330 * Upon reading BOOT_CFG register the following map is done:
331 * Bit 11 and 12 of BOOT_CFG register can determine the current
332 * mmc port
333 * 0x1 SD1
334 * 0x2 SD2
335 * 0x3 SD4
336 */
337
338 switch (reg & 0x3) {
339 case 0x1:
340 imx_iomux_v3_setup_multiple_pads(
341 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
342 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
343 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
344 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
345 break;
346 case 0x3:
347 imx_iomux_v3_setup_multiple_pads(
348 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
349 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
350 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
351 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
352 break;
353 }
354
355 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
356#endif
357
358}
359#endif
360
361
362/*
363 * Do not overwrite the console
364 * Use always serial for U-Boot console
365 */
366int overwrite_console(void)
367{
368 return 1;
369}
370
371int board_eth_init(bd_t *bis)
372{
373 setup_iomux_enet();
374 enable_enet_clk(1);
375
376 return cpu_eth_init(bis);
377}
378
379int board_early_init_f(void)
380{
381
382 setup_iomux_uart();
383 setup_spi();
384
385 return 0;
386}
387
388int board_init(void)
389{
390 /* address of boot parameters */
391 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
392
393 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
394 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
395
396 return 0;
397}
398
399int power_init_board(void)
400{
401 struct pmic *p;
402 int ret;
403 unsigned int reg;
404
405 ret = power_pfuze100_init(I2C_PMIC);
406 if (ret)
407 return ret;
408
409 p = pmic_get("PFUZE100");
410 ret = pmic_probe(p);
411 if (ret)
412 return ret;
413
414 pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
415 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
416
417 /* Increase VGEN3 from 2.5 to 2.8V */
418 pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
419 reg &= ~LDO_VOL_MASK;
420 reg |= LDOB_2_80V;
421 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
422
423 /* Increase VGEN5 from 2.8 to 3V */
424 pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
425 reg &= ~LDO_VOL_MASK;
426 reg |= LDOB_3_00V;
427 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
428
429 /* Set SW1AB stanby volage to 0.975V */
430 pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
431 reg &= ~SW1x_STBY_MASK;
432 reg |= SW1x_0_975V;
433 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
434
435 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
436 pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
437 reg &= ~SW1xCONF_DVSSPEED_MASK;
438 reg |= SW1xCONF_DVSSPEED_4US;
439 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
440
441 /* Set SW1C standby voltage to 0.975V */
442 pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
443 reg &= ~SW1x_STBY_MASK;
444 reg |= SW1x_0_975V;
445 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
446
447 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
448 pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
449 reg &= ~SW1xCONF_DVSSPEED_MASK;
450 reg |= SW1xCONF_DVSSPEED_4US;
451 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
452
453 return 0;
454}
455
456#ifdef CONFIG_CMD_BMODE
457static const struct boot_mode board_boot_modes[] = {
458 /* 4 bit bus width */
459 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
460 /* 8 bit bus width */
461 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
462 {NULL, 0},
463};
464#endif
465
466int board_late_init(void)
467{
468#ifdef CONFIG_CMD_BMODE
469 add_board_boot_modes(board_boot_modes);
470#endif
471
Simon Glass6a38e412017-08-03 12:22:09 -0600472 env_set("board_name", BOARD_NAME);
Stefano Babic4c8d4122016-06-06 11:19:42 +0200473 return 0;
474}
475
476int checkboard(void)
477{
478 puts("Board: ");
479 puts(BOARD_NAME "\n");
480
481 return 0;
482}
483
484#ifdef CONFIG_SPL_BUILD
485#include <spl.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +0900486#include <linux/libfdt.h>
Stefano Babic4c8d4122016-06-06 11:19:42 +0200487
488const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
489 .dram_sdclk_0 = 0x00020030,
490 .dram_sdclk_1 = 0x00020030,
491 .dram_cas = 0x00020030,
492 .dram_ras = 0x00020030,
493 .dram_reset = 0x00020030,
494 .dram_sdcke0 = 0x00003000,
495 .dram_sdcke1 = 0x00003000,
496 .dram_sdba2 = 0x00000000,
497 .dram_sdodt0 = 0x00003030,
498 .dram_sdodt1 = 0x00003030,
499 .dram_sdqs0 = 0x00000030,
500 .dram_sdqs1 = 0x00000030,
501 .dram_sdqs2 = 0x00000030,
502 .dram_sdqs3 = 0x00000030,
503 .dram_sdqs4 = 0x00000030,
504 .dram_sdqs5 = 0x00000030,
505 .dram_sdqs6 = 0x00000030,
506 .dram_sdqs7 = 0x00000030,
507 .dram_dqm0 = 0x00020030,
508 .dram_dqm1 = 0x00020030,
509 .dram_dqm2 = 0x00020030,
510 .dram_dqm3 = 0x00020030,
511 .dram_dqm4 = 0x00020030,
512 .dram_dqm5 = 0x00020030,
513 .dram_dqm6 = 0x00020030,
514 .dram_dqm7 = 0x00020030,
515};
516
517const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
518 .grp_ddr_type = 0x000C0000,
519 .grp_ddrmode_ctl = 0x00020000,
520 .grp_ddrpke = 0x00000000,
521 .grp_addds = 0x00000030,
522 .grp_ctlds = 0x00000030,
523 .grp_ddrmode = 0x00020000,
524 .grp_b0ds = 0x00000030,
525 .grp_b1ds = 0x00000030,
526 .grp_b2ds = 0x00000030,
527 .grp_b3ds = 0x00000030,
528 .grp_b4ds = 0x00000030,
529 .grp_b5ds = 0x00000030,
530 .grp_b6ds = 0x00000030,
531 .grp_b7ds = 0x00000030,
532};
533
534const struct mx6_mmdc_calibration mx6_mmcd_calib = {
535 .p0_mpwldectrl0 = 0x001F001F,
536 .p0_mpwldectrl1 = 0x001F001F,
537 .p1_mpwldectrl0 = 0x00440044,
538 .p1_mpwldectrl1 = 0x00440044,
539 .p0_mpdgctrl0 = 0x434B0350,
540 .p0_mpdgctrl1 = 0x034C0359,
541 .p1_mpdgctrl0 = 0x434B0350,
542 .p1_mpdgctrl1 = 0x03650348,
543 .p0_mprddlctl = 0x4436383B,
544 .p1_mprddlctl = 0x39393341,
545 .p0_mpwrdlctl = 0x35373933,
546 .p1_mpwrdlctl = 0x48254A36,
547};
548
549/* MT41K128M16JT-125 */
550static struct mx6_ddr3_cfg mem_ddr = {
551 .mem_speed = 1600,
552 .density = 2,
553 .width = 16,
554 .banks = 8,
555 .rowaddr = 14,
556 .coladdr = 10,
557 .pagesz = 2,
558 .trcd = 1375,
559 .trcmin = 4875,
560 .trasmin = 3500,
561};
562
563static void ccgr_init(void)
564{
565 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
566
567 writel(0x00C03F3F, &ccm->CCGR0);
568 writel(0x0030FC03, &ccm->CCGR1);
569 writel(0x0FFFC000, &ccm->CCGR2);
570 writel(0x3FF00000, &ccm->CCGR3);
571 writel(0x00FFF300, &ccm->CCGR4);
572 writel(0x0F0000C3, &ccm->CCGR5);
573 writel(0x000003FF, &ccm->CCGR6);
574}
575
Stefano Babic4c8d4122016-06-06 11:19:42 +0200576/*
577 * This section requires the differentiation between iMX6 Sabre boards, but
578 * for now, it will configure only for the mx6q variant.
579 */
580static void spl_dram_init(void)
581{
582 struct mx6_ddr_sysinfo sysinfo = {
583 /* width of data bus:0=16,1=32,2=64 */
584 .dsize = 2,
585 /* config for full 4GB range so that get_mem_size() works */
586 .cs_density = 32, /* 32Gb per CS */
587 /* single chip select */
588 .ncs = 1,
589 .cs1_mirror = 0,
590 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
591 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
592 .walat = 1, /* Write additional latency */
593 .ralat = 5, /* Read additional latency */
594 .mif3_mode = 3, /* Command prediction working mode */
595 .bi_on = 1, /* Bank interleaving enabled */
596 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
597 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
598 .ddr_type = DDR_TYPE_DDR3,
Fabio Estevamcb3c1212016-08-29 20:37:15 -0300599 .refsel = 1, /* Refresh cycles at 32KHz */
600 .refr = 7, /* 8 refresh commands per refresh cycle */
Stefano Babic4c8d4122016-06-06 11:19:42 +0200601 };
602
603 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
604 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
605}
606
607void board_init_f(ulong dummy)
608{
609 /* setup AIPS and disable watchdog */
610 arch_cpu_init();
611
612 ccgr_init();
613 gpr_init();
614
615 /* iomux and setup of i2c */
616 board_early_init_f();
617
618 /* setup GP timer */
619 timer_init();
620
621 /* UART clocks enabled and gd valid - init serial console */
622 preloader_console_init();
623
624 /* DDR initialization */
625 spl_dram_init();
626
627 /* Clear the BSS. */
628 memset(__bss_start, 0, __bss_end - __bss_start);
629
630 /* load/boot image from boot device */
631 board_init_r(NULL, 0);
632}
633
634#endif