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git01.mediatek.com / filogic / uboot / 1e04cae775510059dee8d97e1c7788300ec80532 / . / arch / arm / include / asm / arch-s5pc1xx / gpio.h
blob: 76b901b3977bbc5110f45ad47546400e479775ed [file] [log] [blame]
Minkyu Kang87649982009-10-01 17:20:01 +0900[diff] [blame]1/*
2 * (C) Copyright 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_GPIO_H
22#define __ASM_ARCH_GPIO_H
23
24#ifndef __ASSEMBLY__
Minkyu Kangedec1dc2010-03-24 15:31:06 +0900[diff] [blame]25struct s5p_gpio_bank {
Minkyu Kangc6cb1842009-10-15 11:19:15 +0900[diff] [blame]26 unsigned int con;
27 unsigned int dat;
28 unsigned int pull;
29 unsigned int drv;
30 unsigned int pdn_con;
31 unsigned int pdn_pull;
Minkyu Kang87649982009-10-01 17:20:01 +0900[diff] [blame]32 unsigned char res1[8];
33};
34
35struct s5pc100_gpio {
Minkyu Kangfc62ca82010-08-25 13:45:43 +0900[diff] [blame]36 struct s5p_gpio_bank a0;
37 struct s5p_gpio_bank a1;
38 struct s5p_gpio_bank b;
39 struct s5p_gpio_bank c;
40 struct s5p_gpio_bank d;
41 struct s5p_gpio_bank e0;
42 struct s5p_gpio_bank e1;
43 struct s5p_gpio_bank f0;
44 struct s5p_gpio_bank f1;
45 struct s5p_gpio_bank f2;
46 struct s5p_gpio_bank f3;
47 struct s5p_gpio_bank g0;
48 struct s5p_gpio_bank g1;
49 struct s5p_gpio_bank g2;
50 struct s5p_gpio_bank g3;
51 struct s5p_gpio_bank i;
52 struct s5p_gpio_bank j0;
53 struct s5p_gpio_bank j1;
54 struct s5p_gpio_bank j2;
55 struct s5p_gpio_bank j3;
56 struct s5p_gpio_bank j4;
57 struct s5p_gpio_bank k0;
58 struct s5p_gpio_bank k1;
59 struct s5p_gpio_bank k2;
60 struct s5p_gpio_bank k3;
61 struct s5p_gpio_bank l0;
62 struct s5p_gpio_bank l1;
63 struct s5p_gpio_bank l2;
64 struct s5p_gpio_bank l3;
65 struct s5p_gpio_bank l4;
66 struct s5p_gpio_bank h0;
67 struct s5p_gpio_bank h1;
68 struct s5p_gpio_bank h2;
69 struct s5p_gpio_bank h3;
Minkyu Kang87649982009-10-01 17:20:01 +0900[diff] [blame]70};
71
72struct s5pc110_gpio {
Minkyu Kangfc62ca82010-08-25 13:45:43 +0900[diff] [blame]73 struct s5p_gpio_bank a0;
74 struct s5p_gpio_bank a1;
75 struct s5p_gpio_bank b;
76 struct s5p_gpio_bank c0;
77 struct s5p_gpio_bank c1;
78 struct s5p_gpio_bank d0;
79 struct s5p_gpio_bank d1;
80 struct s5p_gpio_bank e0;
81 struct s5p_gpio_bank e1;
82 struct s5p_gpio_bank f0;
83 struct s5p_gpio_bank f1;
84 struct s5p_gpio_bank f2;
85 struct s5p_gpio_bank f3;
86 struct s5p_gpio_bank g0;
87 struct s5p_gpio_bank g1;
88 struct s5p_gpio_bank g2;
89 struct s5p_gpio_bank g3;
90 struct s5p_gpio_bank i;
91 struct s5p_gpio_bank j0;
92 struct s5p_gpio_bank j1;
93 struct s5p_gpio_bank j2;
94 struct s5p_gpio_bank j3;
95 struct s5p_gpio_bank j4;
96 struct s5p_gpio_bank mp0_1;
97 struct s5p_gpio_bank mp0_2;
98 struct s5p_gpio_bank mp0_3;
99 struct s5p_gpio_bank mp0_4;
100 struct s5p_gpio_bank mp0_5;
101 struct s5p_gpio_bank mp0_6;
102 struct s5p_gpio_bank mp0_7;
103 struct s5p_gpio_bank mp1_0;
104 struct s5p_gpio_bank mp1_1;
105 struct s5p_gpio_bank mp1_2;
106 struct s5p_gpio_bank mp1_3;
107 struct s5p_gpio_bank mp1_4;
108 struct s5p_gpio_bank mp1_5;
109 struct s5p_gpio_bank mp1_6;
110 struct s5p_gpio_bank mp1_7;
111 struct s5p_gpio_bank mp1_8;
112 struct s5p_gpio_bank mp2_0;
113 struct s5p_gpio_bank mp2_1;
114 struct s5p_gpio_bank mp2_2;
115 struct s5p_gpio_bank mp2_3;
116 struct s5p_gpio_bank mp2_4;
117 struct s5p_gpio_bank mp2_5;
118 struct s5p_gpio_bank mp2_6;
119 struct s5p_gpio_bank mp2_7;
120 struct s5p_gpio_bank mp2_8;
Minkyu Kangedec1dc2010-03-24 15:31:06 +0900[diff] [blame]121 struct s5p_gpio_bank res1[48];
Minkyu Kangfc62ca82010-08-25 13:45:43 +0900[diff] [blame]122 struct s5p_gpio_bank h0;
123 struct s5p_gpio_bank h1;
124 struct s5p_gpio_bank h2;
125 struct s5p_gpio_bank h3;
Minkyu Kang87649982009-10-01 17:20:01 +0900[diff] [blame]126};
Minkyu Kang1edf0f22010-02-12 18:17:52 +0900[diff] [blame]127
128/* functions */
Łukasz Majewski4d954cc2011-07-15 00:16:22 +0000[diff] [blame]129void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
130void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
131void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
132void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
133unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
134void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
135void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
136void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
Łukasz Majewski1e04cae2011-08-22 22:34:58 +0000[diff] [blame^]137
138/* GPIO pins per bank */
139#define GPIO_PER_BANK 8
140
141static inline unsigned int s5p_gpio_base(int nr)
142{
143 return S5PC110_GPIO_BASE;
144}
145
146#define s5pc110_gpio_get_nr(bank, pin) \
147 ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
148 - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
149 * GPIO_PER_BANK) + pin)
Minkyu Kang87649982009-10-01 17:20:01 +0900[diff] [blame]150#endif
151
Minkyu Kang1edf0f22010-02-12 18:17:52 +0900[diff] [blame]152/* Pin configurations */
153#define GPIO_INPUT 0x0
154#define GPIO_OUTPUT 0x1
155#define GPIO_IRQ 0xf
156#define GPIO_FUNC(x) (x)
157
158/* Pull mode */
159#define GPIO_PULL_NONE 0x0
160#define GPIO_PULL_DOWN 0x1
161#define GPIO_PULL_UP 0x2
162
163/* Drive Strength level */
164#define GPIO_DRV_1X 0x0
Chander Kashyapb26418c2011-04-18 00:08:43 +0000[diff] [blame]165#define GPIO_DRV_3X 0x1
166#define GPIO_DRV_2X 0x2
Minkyu Kang1edf0f22010-02-12 18:17:52 +0900[diff] [blame]167#define GPIO_DRV_4X 0x3
168#define GPIO_DRV_FAST 0x0
169#define GPIO_DRV_SLOW 0x1
170
Minkyu Kang87649982009-10-01 17:20:01 +0900[diff] [blame]171#endif