| Peter Senna Tschudin | 56d9692 | 2017-11-06 19:14:11 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2015 General Electric Company |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef __PPD_GPIO_H_ |
| 8 | #define __PPD_GPIO_H_ |
| 9 | |
| 10 | #include <asm/arch/iomux-mx53.h> |
| 11 | #include <asm/gpio.h> |
| 12 | |
| 13 | #define PPD_UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ |
| 14 | PAD_CTL_PUS_100K_UP) |
| 15 | |
| 16 | static const iomux_v3_cfg_t ppd_pads[] = { |
| 17 | /* FEC */ |
| 18 | MX53_PAD_EIM_A22__GPIO2_16, |
| 19 | /* UART */ |
| 20 | NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, PPD_UART_PAD_CTRL), |
| 21 | NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, PPD_UART_PAD_CTRL), |
| 22 | /* Video */ |
| 23 | MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */ |
| 24 | MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */ |
| 25 | MX53_PAD_CSI0_DAT10__GPIO5_28, /* DATA_WIDTH_CTRL */ |
| 26 | MX53_PAD_CSI0_PIXCLK__GPIO5_18, /* HOST_CONTROLLED_RESET_TO_LCD_N */ |
| 27 | MX53_PAD_EIM_DA2__GPIO3_2, /* LVDS1_MUX_CTRL */ |
| 28 | MX53_PAD_EIM_DA3__GPIO3_3, /* LVDS0_MUX_CTRL */ |
| 29 | MX53_PAD_EIM_A21__GPIO2_17, /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ |
| 30 | MX53_PAD_CSI0_DAT11__GPIO5_29, /* BACKLIGHT_ENABLE */ |
| 31 | MX53_PAD_DISP0_DAT9__PWM2_PWMO, /* IMX535_PWM2_TO_LCD_CONNECTOR */ |
| 32 | /* I2C */ |
| 33 | MX53_PAD_EIM_A20__GPIO2_18, /* RESET_I2C1_BUS_SEGMENT_MUX_N */ |
| 34 | |
| 35 | /* SPI */ |
| 36 | MX53_PAD_DISP0_DAT23__GPIO5_17, |
| 37 | MX53_PAD_KEY_COL2__GPIO4_10, |
| 38 | MX53_PAD_KEY_ROW2__GPIO4_11, |
| 39 | MX53_PAD_KEY_COL3__GPIO4_12, |
| 40 | }; |
| 41 | |
| 42 | struct gpio_cfg { |
| 43 | unsigned int gpio; |
| 44 | int value; |
| 45 | }; |
| 46 | |
| 47 | #define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16) |
| 48 | #define UD_SCAN_CTRL IMX_GPIO_NR(5, 21) |
| 49 | #define LR_SCAN_CTRL IMX_GPIO_NR(5, 20) |
| 50 | #define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3) |
| 51 | #define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2) |
| 52 | #define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18) |
| 53 | #define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28) |
| 54 | #define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28) |
| 55 | #define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29) |
| 56 | #define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22) |
| 57 | #define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27) |
| 58 | #define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17) |
| 59 | #define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29) |
| 60 | #define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18) |
| 61 | #define ECSPI1_CS0 IMX_GPIO_NR(5, 17) |
| 62 | #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) |
| 63 | #define ECSPI1_CS2 IMX_GPIO_NR(4, 11) |
| 64 | #define ECSPI1_CS3 IMX_GPIO_NR(4, 12) |
| 65 | |
| 66 | static const struct gpio_cfg ppd_gpios[] = { |
| 67 | /* FEC */ |
| 68 | /* Drive Low as GPIO output for 25ms per Eth Phy IX spec */ |
| 69 | /* Then Drive High as GPIO output to bring Eth Phy IC out of reset */ |
| 70 | { RESET_IMX535_ETHERNET_PHY_N, 0 }, |
| 71 | { RESET_IMX535_ETHERNET_PHY_N, 1 }, |
| 72 | /* Video */ |
| 73 | { UD_SCAN_CTRL, 0 }, |
| 74 | { LR_SCAN_CTRL, 1 }, |
| 75 | #ifdef PROPRIETARY_CHANGES |
| 76 | { LVDS0_MUX_CTRL, 1 }, |
| 77 | #else |
| 78 | { LVDS0_MUX_CTRL, 0 }, |
| 79 | #endif |
| 80 | { LVDS1_MUX_CTRL, 1 }, |
| 81 | { HOST_CONTROLLED_RESET_TO_LCD_N, 1 }, |
| 82 | { DATA_WIDTH_CTRL, 0 }, |
| 83 | { RESET_DP0_TRANSMITTER_N, 1 }, |
| 84 | { RESET_DP1_TRANSMITTER_N, 1 }, |
| 85 | { POWER_DOWN_LVDS0_DESERIALIZER_N, 1 }, |
| 86 | { POWER_DOWN_LVDS1_DESERIALIZER_N, 1 }, |
| 87 | { ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 }, |
| 88 | { BACKLIGHT_ENABLE, 0 }, |
| 89 | { RESET_I2C1_BUS_SEGMENT_MUX_N, 1 }, |
| 90 | { ECSPI1_CS0, 1 }, |
| 91 | { ECSPI1_CS1, 1 }, |
| 92 | { ECSPI1_CS2, 1 }, |
| 93 | { ECSPI1_CS3, 1 }, |
| 94 | }; |
| 95 | |
| 96 | #endif /* __PPD_GPIO_H_ */ |