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git01.mediatek.com / filogic / uboot / c95153904fb389c256a58af4e77ce385419ba988 / . / board / freescale / mx6memcal / Kconfig
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Eric Nelson4c644792017-12-11 13:52:11 -0200[diff] [blame]1if TARGET_MX6MEMCAL
2
3config SYS_BOARD
4 default "mx6memcal"
5
6config SYS_VENDOR
7 default "freescale"
8
9config SYS_CONFIG_NAME
10 default "mx6memcal"
11
12menu "mx6memcal specifics"
13choice
14 prompt "Serial console"
15 help
16 Either UART1 or UART2 will be used as the console for
17 displaying the calibration values or errors.
18
19config SERIAL_CONSOLE_UART1
20 bool "UART1"
21 help
22 Select this if your board uses UART1 for its' console.
23
24config SERIAL_CONSOLE_UART2
25 bool "UART2"
26 help
27 Select this if your board uses UART2 for its' console.
28
29endchoice
30
31choice
32 prompt "UART pads"
33 help
34 Select the RX and TX pads used for your serial console.
35 The choices below reflect the most commonly used options
36 for your UART.
37
38 config UART2_EIM_D26_27
39 bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
40 depends on SERIAL_CONSOLE_UART2
41 help
42 Choose this configuration if you're using pads
43 EIM_D26 and D27 for a console on UART2.
44 This is typical for designs that are based on the
45 NXP SABRELite.
46
47 config UART1_CSI0_DAT10_11
48 bool "UART1 on CSI0_DAT10/11 (Wand)"
49 depends on SERIAL_CONSOLE_UART1
50 help
51 Choose this configuration if you're using pads
52 CSI0_DAT10 and DAT11 for a console on UART1 as
53 is done on the i.MX6 Wand board.
54
55 config UART1_SD3_DAT6_7
56 bool "UART1 on SD3_DAT6/7 (SabreSD, SabreAuto)"
57 depends on SERIAL_CONSOLE_UART1
58 help
59 Choose this configuration if you're using pads
60 SD3_DAT6 and DAT7 for a console on UART1 as is
61 done on the NXP SABRESD or SABREAUTO designs.
62
63 config UART1_UART1
64 bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
65 depends on SERIAL_CONSOLE_UART1
66 help
67 Choose this configuration if you're using pads
68 UART1_TXD/RXD for a console on UART1 as is done
69 on most i.MX6SL designs.
70
71endchoice
72
73config IMXIMAGE_OUTPUT
74 bool "Include output for imximage .cfg files"
75 default y
76 help
77 Say "Y" if you want output formatted for use in non-SPL
78 (DCD-style) configuration files.
79
80config DDRWIDTH
81 int "DDR bus width"
82 default 64
83 help
84 Select either 32 or 64 to reflect the DDR bus width.
85
86config DDRCS
87 int "DDR chip selects"
88 default 2
89 range 1 2
90 help
91 Select the number of chip selects used in your board design
92
93choice
94 prompt "Memory type"
95 help
96 Select the type of DDR (DDR3 or LPDDR2) used on your design
97
98config DDR3
99 bool "DDR3"
100 help
101 Select this if your board design uses DDR3.
102
103config LPDDR2
104 bool "LPDDR2"
105 help
106 Select this if your board design uses LPDDR2.
107
108endchoice
109
110choice
111 prompt "Memory device"
112
113config MT41K512M16TNA
114 bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)"
115 depends on DDR3
116
117config MT41K128M16JT
118 bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)"
119 depends on DDR3
120
121config H5TQ4G63AFR
122 bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)"
123 depends on DDR3
124
125config H5TQ2G63DFR
126 bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)"
127 depends on DDR3
128
129config MT42L256M32D2LG
130 bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
131 depends on LPDDR2
132
133config MT29PZZZ4D4BKESK
134 bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
135 depends on LPDDR2
136
137endchoice
138
139config DDR_ODT
140 int "DDR On-die-termination"
141 default 2
142 range 0 7
143 help
144 Enter the on-die termination value as an index defined for
145 IOMUX settings for PAD_DRAM_SDCLK0_P and others.
146 0 == Disabled
147 1 == 120 Ohm
148 2 == 60 Ohm
149 3 == 40 Ohm
150 4 == 30 Ohm
151 5 == 24 Ohm
152 6 == 20 Ohm
153 7 == 17 Ohm
154 Value will be applied to all clock and data lines
155
156
157config DRAM_DRIVE_STRENGTH
158 int "DRAM Drive strength"
159 default 6
160 range 0 7
161 help
162 Enter drive strength as an index defined for IOMUX settings
163 for GRP_B1DS and others.
164 0 == Hi Z
165 6 == 40 Ohm (default)
166 7 == 34 Ohm
167 Value will be applied to all clock and data lines
168
169config RTT_NOM
170 int "RTT_NOM"
171 default 1
172 range 1 2
173 help
174 Enter the RTT_NOM selector
175 1 == RZQ/4 (60ohm)
176 2 == RZQ/2 (120ohm)
177
178config RTT_WR
179 int "RTT_WR"
180 default 1
181 range 0 2
182 help
183 Enter the RTT_WR selector for MR2
184 0 == Dynamic ODT disabled
185 1 == RZQ/4 (60ohm)
186 2 == RZQ/2 (120ohm)
187
188config RALAT
189 int "Read additional latency"
190 default 5
191 range 0 7
192 help
193 Enter a latency in number of cycles. This will be added to
194 CAS and internal delays for which the MMDC will retrieve the
195 read data from the internal FIFO.
196 This is used to compensate for board/chip delays.
197
198config WALAT
199 int "Write additional latency"
200 default 0
201 range 0 7
202 help
203 Enter a latency in number of cycles. This will be added to
204 CAS and internal delays for which the MMDC will retrieve the
205 read data from the internal FIFO
206 This is used to compensate for board/chip delays.
207
208config REFSEL
209 int "Refresh period"
210 range 0 3
211 default 1
212 help
213 Select the DDR refresh period.
214 See the description of bitfield REF_SEL in the reference manual
215 for details.
216 0 == disabled
217 1 == 32 kHz
218 2 == 64 kHz
219 3 == fast counter
220
221config REFR
222 int "Number of refreshes"
223 range 0 7
224 default 7
225 help
226 This selects the number of refreshes (-1) during each period.
227 i.e.:
228 0 == 1 refresh (tRFC)
229 7 == 8 refreshes (tRFC*8)
230 See the description of MDREF[REFR] in the reference manual for
231 details.
232
233endmenu
234endif
235