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git01.mediatek.com / filogic / uboot / 196b1efd55b71dfc6baca103fe8cdd8d56dea834 / . / drivers / net / qe / uccf.h
blob: 99f8458edf67613f8d94ec84aaf84fe37fddb9f7 [file] [log] [blame]
Heiko Schocher41b64a82020-02-06 09:48:16 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 *
5 * Dave Liu <daveliu@freescale.com>
6 * based on source code of Shlomi Gridish
7 */
8
9#ifndef __UCCF_H__
10#define __UCCF_H__
11
12#include "common.h"
13#include "linux/immap_qe.h"
14#include <fsl_qe.h>
15
16/* Fast or Giga ethernet */
17enum enet_type {
18 FAST_ETH,
19 GIGA_ETH,
20};
21
22/* General UCC Extended Mode Register */
23#define UCC_GUEMR_MODE_MASK_RX 0x02
24#define UCC_GUEMR_MODE_MASK_TX 0x01
25#define UCC_GUEMR_MODE_FAST_RX 0x02
26#define UCC_GUEMR_MODE_FAST_TX 0x01
27#define UCC_GUEMR_MODE_SLOW_RX 0x00
28#define UCC_GUEMR_MODE_SLOW_TX 0x00
29/* Bit 3 must be set 1 */
30#define UCC_GUEMR_SET_RESERVED3 0x10
31
32/* General UCC FAST Mode Register */
33#define UCC_FAST_GUMR_TCI 0x20000000
34#define UCC_FAST_GUMR_TRX 0x10000000
35#define UCC_FAST_GUMR_TTX 0x08000000
36#define UCC_FAST_GUMR_CDP 0x04000000
37#define UCC_FAST_GUMR_CTSP 0x02000000
38#define UCC_FAST_GUMR_CDS 0x01000000
39#define UCC_FAST_GUMR_CTSS 0x00800000
40#define UCC_FAST_GUMR_TXSY 0x00020000
41#define UCC_FAST_GUMR_RSYN 0x00010000
42#define UCC_FAST_GUMR_RTSM 0x00002000
43#define UCC_FAST_GUMR_REVD 0x00000400
44#define UCC_FAST_GUMR_ENR 0x00000020
45#define UCC_FAST_GUMR_ENT 0x00000010
46
47/* GUMR [MODE] bit maps */
48#define UCC_FAST_GUMR_HDLC 0x00000000
49#define UCC_FAST_GUMR_QMC 0x00000002
50#define UCC_FAST_GUMR_UART 0x00000004
51#define UCC_FAST_GUMR_BISYNC 0x00000008
52#define UCC_FAST_GUMR_ATM 0x0000000a
53#define UCC_FAST_GUMR_ETH 0x0000000c
54
55/* Transmit On Demand (UTORD) */
56#define UCC_SLOW_TOD 0x8000
57#define UCC_FAST_TOD 0x8000
58
59/* Fast Ethernet (10/100 Mbps) */
60/* Rx virtual FIFO size */
61#define UCC_GETH_URFS_INIT 512
62/* 1/2 urfs */
63#define UCC_GETH_URFET_INIT 256
64/* 3/4 urfs */
65#define UCC_GETH_URFSET_INIT 384
66/* Tx virtual FIFO size */
67#define UCC_GETH_UTFS_INIT 512
68/* 1/2 utfs */
69#define UCC_GETH_UTFET_INIT 256
70#define UCC_GETH_UTFTT_INIT 128
71
72/* Gigabit Ethernet (1000 Mbps) */
73/* Rx virtual FIFO size */
74#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/
75/* 1/2 urfs */
76#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/
77/* 3/4 urfs */
78#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/
79/* Tx virtual FIFO size */
80#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/
81/* 1/2 utfs */
82#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/
83#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/
84
85/* UCC fast alignment */
86#define UCC_FAST_RX_ALIGN 4
87#define UCC_FAST_MRBLR_ALIGNMENT 4
88#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
89
90/* Sizes */
91#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8
92
93/* UCC fast structure. */
94struct ucc_fast_inf {
95 int ucc_num;
96 qe_clock_e rx_clock;
97 qe_clock_e tx_clock;
98 enum enet_type eth_type;
99};
100
101struct ucc_fast_priv {
102 struct ucc_fast_inf *uf_info;
103 ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */
104 u32 *p_ucce; /* a pointer to the event register */
105 u32 *p_uccm; /* a pointer to the mask register */
106 int enabled_tx; /* whether UCC is enabled for Tx (ENT) */
107 int enabled_rx; /* whether UCC is enabled for Rx (ENR) */
108 u32 ucc_fast_tx_virtual_fifo_base_offset;
109 u32 ucc_fast_rx_virtual_fifo_base_offset;
110};
111
112void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf);
113u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
114void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode);
115void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode);
116int ucc_fast_init(struct ucc_fast_inf *uf_info,
117 struct ucc_fast_priv **uccf_ret);
118
119#endif /* __UCCF_H__ */