| Bin Meng | 81da5a8 | 2015-02-02 22:35:27 +0800 | [diff] [blame] | 1 | # |
| 2 | # Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
| 3 | # |
| 4 | # SPDX-License-Identifier: GPL-2.0+ |
| 5 | # |
| 6 | |
| 7 | config INTEL_QUARK |
| 8 | bool |
| 9 | select HAVE_RMU |
| Bin Meng | 6f40e7c | 2017-07-30 06:23:13 -0700 | [diff] [blame^] | 10 | select ARCH_EARLY_INIT_R |
| Bin Meng | b0d42d7 | 2017-07-30 06:23:12 -0700 | [diff] [blame] | 11 | select ARCH_MISC_INIT |
| Bin Meng | 81da5a8 | 2015-02-02 22:35:27 +0800 | [diff] [blame] | 12 | |
| 13 | if INTEL_QUARK |
| 14 | |
| 15 | config HAVE_RMU |
| 16 | bool "Add a Remote Management Unit (RMU) binary" |
| 17 | help |
| 18 | Select this option to add a Remote Management Unit (RMU) binary |
| 19 | to the resulting U-Boot image. It is a data block (up to 64K) of |
| 20 | machine-specific code which must be put in the flash for the RMU |
| 21 | within the Quark SoC processor to access when powered up before |
| 22 | system BIOS is executed. |
| 23 | |
| 24 | config RMU_FILE |
| 25 | string "Remote Management Unit (RMU) binary filename" |
| 26 | depends on HAVE_RMU |
| 27 | default "rmu.bin" |
| 28 | help |
| 29 | The filename of the file to use as Remote Management Unit (RMU) |
| 30 | binary in the board directory. |
| 31 | |
| 32 | config RMU_ADDR |
| 33 | hex "Remote Management Unit (RMU) binary location" |
| 34 | depends on HAVE_RMU |
| 35 | default 0xfff00000 |
| 36 | help |
| 37 | The location of the RMU binary is determined by a strap. It must be |
| 38 | put in flash at a location matching the strap-determined base address. |
| 39 | |
| 40 | The default base address of 0xfff00000 indicates that the binary must |
| 41 | be located at offset 0 from the beginning of a 1MB flash device. |
| 42 | |
| 43 | config HAVE_CMC |
| 44 | bool |
| 45 | default HAVE_RMU |
| 46 | |
| 47 | config CMC_FILE |
| 48 | string |
| 49 | depends on HAVE_CMC |
| 50 | default RMU_FILE |
| 51 | |
| 52 | config CMC_ADDR |
| 53 | hex |
| 54 | depends on HAVE_CMC |
| 55 | default RMU_ADDR |
| 56 | |
| 57 | config ESRAM_BASE |
| 58 | hex |
| 59 | default 0x80000000 |
| 60 | help |
| 61 | Embedded SRAM (eSRAM) memory-mapped base address. |
| 62 | |
| 63 | config PCIE_ECAM_BASE |
| 64 | hex |
| 65 | default 0xe0000000 |
| 66 | |
| 67 | config RCBA_BASE |
| 68 | hex |
| 69 | default 0xfed1c000 |
| 70 | help |
| 71 | Root Complex register block memory-mapped base address. |
| 72 | |
| 73 | config ACPI_PM1_BASE |
| 74 | hex |
| 75 | default 0x1000 |
| 76 | help |
| 77 | ACPI Power Managment 1 (PM1) i/o-mapped base address. |
| 78 | This device is defined in ACPI specification, with 16 bytes in size. |
| 79 | |
| 80 | config ACPI_PBLK_BASE |
| 81 | hex |
| 82 | default 0x1010 |
| 83 | help |
| 84 | ACPI Processor Block (PBLK) i/o-mapped base address. |
| 85 | This device is defined in ACPI specification, with 16 bytes in size. |
| 86 | |
| 87 | config SPI_DMA_BASE |
| 88 | hex |
| 89 | default 0x1020 |
| 90 | help |
| 91 | SPI DMA i/o-mapped base address. |
| 92 | |
| 93 | config GPIO_BASE |
| 94 | hex |
| 95 | default 0x1080 |
| 96 | help |
| 97 | GPIO i/o-mapped base address. |
| 98 | |
| 99 | config ACPI_GPE0_BASE |
| 100 | hex |
| 101 | default 0x1100 |
| 102 | help |
| 103 | ACPI General Purpose Event 0 (GPE0) i/o-mapped base address. |
| 104 | This device is defined in ACPI specification, with 64 bytes in size. |
| 105 | |
| 106 | config WDT_BASE |
| 107 | hex |
| 108 | default 0x1140 |
| 109 | help |
| 110 | Watchdog timer i/o-mapped base address. |
| 111 | |
| 112 | config SYS_CAR_ADDR |
| 113 | hex |
| 114 | default ESRAM_BASE |
| 115 | |
| 116 | config SYS_CAR_SIZE |
| 117 | hex |
| 118 | default 0x8000 |
| 119 | help |
| 120 | Space in bytes in eSRAM used as Cache-As-ARM (CAR). |
| 121 | Note this size must not exceed eSRAM's total size. |
| 122 | |
| Bin Meng | 81da5a8 | 2015-02-02 22:35:27 +0800 | [diff] [blame] | 123 | endif |