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git01.mediatek.com / filogic / uboot / 18eceae2e821506e0e93f407a1be94205f65ee03 / . / arch / arm / dts / imx8mm-cl-iot-gate-u-boot.dtsi
blob: 1878c4e13fbea20178b8945cdc3504539f0df8ae [file] [log] [blame]
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
Marcel Ziswiler9888e122021-10-23 01:15:12 +0200[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]8/ {
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]9 firmware {
10 optee {
11 compatible = "linaro,optee-tz";
12 method = "smc";
13 };
14 };
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]15
16 wdt-reboot {
17 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]19 wdt = <&wdog1>;
20 };
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]21};
22
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]23&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]25};
26
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]27&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]29};
30
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]31&fec1 {
32 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
33};
34
35&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]37};
38
39&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]41};
42
43&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]45};
46
47&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]49};
50
51&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]53};
54
55&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]57};
58
59&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]61};
62
63&pinctrl_i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]65};
66
67&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]69};
70
71&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]73};
74
75&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]77};
78
79&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]81};
82
83&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]85};
86
Peng Fan83a9b282022-06-11 20:21:03 +0800[diff] [blame]87&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Peng Fan83a9b282022-06-11 20:21:03 +0800[diff] [blame]89};
90
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]91&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]93};
94
95&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]97};
98
99&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]101};
102
103&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]105};
106
107&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]109};