Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2005 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 5 | * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
Simon Glass | 18afe10 | 2019-11-14 12:57:47 -0700 | [diff] [blame^] | 8 | #include <init.h> |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 9 | #include <asm/mmu.h> |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 10 | #include <asm/io.h> |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 11 | #include <common.h> |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 12 | #include <mpc83xx.h> |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 13 | #include <pci.h> |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 14 | #include <i2c.h> |
| 15 | #include <asm/fsl_i2c.h> |
Wolfgang Denk | 9559357 | 2009-05-14 23:18:34 +0200 | [diff] [blame] | 16 | |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 17 | static struct pci_region pci1_regions[] = { |
| 18 | { |
| 19 | bus_start: CONFIG_SYS_PCI1_MEM_BASE, |
| 20 | phys_start: CONFIG_SYS_PCI1_MEM_PHYS, |
| 21 | size: CONFIG_SYS_PCI1_MEM_SIZE, |
| 22 | flags: PCI_REGION_MEM | PCI_REGION_PREFETCH |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 23 | }, |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 24 | { |
| 25 | bus_start: CONFIG_SYS_PCI1_IO_BASE, |
| 26 | phys_start: CONFIG_SYS_PCI1_IO_PHYS, |
| 27 | size: CONFIG_SYS_PCI1_IO_SIZE, |
| 28 | flags: PCI_REGION_IO |
| 29 | }, |
| 30 | { |
| 31 | bus_start: CONFIG_SYS_PCI1_MMIO_BASE, |
| 32 | phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, |
| 33 | size: CONFIG_SYS_PCI1_MMIO_SIZE, |
| 34 | flags: PCI_REGION_MEM |
| 35 | }, |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 36 | }; |
| 37 | |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 38 | /* |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 39 | * pci_init_board() |
| 40 | * |
| 41 | * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since |
| 42 | * per TQM834x design physical connections to external devices (PCI sockets) |
| 43 | * are routed only to the PCI1 we do not account for the second one - this code |
| 44 | * supports PCI1 module only. Should support for the PCI2 be required in the |
| 45 | * future it needs a separate pci_controller structure (above) and handling - |
| 46 | * please refer to other boards' implementation for dual PCI host controllers, |
| 47 | * for example board/Marvell/db64360/pci.c, pci_init_board() |
| 48 | * |
| 49 | */ |
| 50 | void |
| 51 | pci_init_board(void) |
| 52 | { |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 53 | volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; |
| 54 | volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; |
| 55 | volatile law83xx_t *pci_law = immr->sysconf.pcilaw; |
| 56 | struct pci_region *reg[] = { pci1_regions }; |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 57 | u32 reg32; |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 58 | |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 59 | /* |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 60 | * Configure PCI controller and PCI_CLK_OUTPUT |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 61 | * |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 62 | * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one |
| 63 | * line actually used for clocking all external PCI devices in TQM83xx. |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 64 | * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 65 | * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 66 | * are known to hang the board; this issue is under investigation |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 67 | * (13 oct 05) |
| 68 | */ |
| 69 | reg32 = OCCR_PCICOE1; |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 70 | #if 0 |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 71 | /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ |
| 72 | reg32 = 0xff000000; |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 73 | #endif |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 74 | if (clk->spmr & SPMR_CKID) { |
Mario Six | d10f318 | 2019-01-21 09:17:53 +0100 | [diff] [blame] | 75 | /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 76 | * fields accordingly */ |
| 77 | reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 78 | |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 79 | reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ |
| 80 | | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ |
| 81 | | OCCR_PCICD6 | OCCR_PCICD7); |
| 82 | } |
| 83 | |
| 84 | clk->occr = reg32; |
| 85 | udelay(2000); |
| 86 | |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 87 | /* Configure PCI Local Access Windows */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; |
Rafal Jaworowski | ce49c27 | 2005-11-17 00:26:18 +0100 | [diff] [blame] | 89 | pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 90 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 91 | pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; |
Rafal Jaworowski | ce49c27 | 2005-11-17 00:26:18 +0100 | [diff] [blame] | 92 | pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 93 | |
Kim Phillips | 57a2af3 | 2009-07-18 18:42:13 -0500 | [diff] [blame] | 94 | udelay(2000); |
Wolfgang Denk | 9559357 | 2009-05-14 23:18:34 +0200 | [diff] [blame] | 95 | |
Peter Tyser | e228332 | 2010-09-14 19:13:50 -0500 | [diff] [blame] | 96 | mpc83xx_pci_init(1, reg); |
Wolfgang Denk | 9559357 | 2009-05-14 23:18:34 +0200 | [diff] [blame] | 97 | } |