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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +00002/*
3 * Embest/Timll DevKit3250 board configuration file
4 *
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +03005 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +00006 */
7
8#ifndef __CONFIG_DEVKIT3250_H__
9#define __CONFIG_DEVKIT3250_H__
10
11/* SoC and board defines */
Alexey Brodkin267d8e22014-02-26 17:47:58 +040012#include <linux/sizes.h>
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000013#include <asm/arch/cpu.h>
14
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000015/*
16 * Memory configurations
17 */
Tom Rinibb4dd962022-11-16 13:10:37 -050018#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
19#define CFG_SYS_SDRAM_SIZE SZ_64M
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000020
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000021/*
Vladimir Zapolskiy936c2002015-12-19 23:41:23 +020022 * DMA
23 */
Vladimir Zapolskiy936c2002015-12-19 23:41:23 +020024
25/*
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030026 * GPIO
27 */
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030028
29/*
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000030 * NOR Flash
31 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050032#define CFG_SYS_FLASH_BASE EMC_CS0_BASE
33#define CFG_SYS_FLASH_SIZE SZ_4M
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000034
35/*
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030036 * NAND controller
37 */
Tom Rinib4213492022-11-12 17:36:51 -050038#define CFG_SYS_NAND_BASE SLC_NAND_BASE
39#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030040
41/*
42 * NAND chip timings
43 */
44#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
45#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
46#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
47#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000
Tom Rini16fb9f82022-12-04 10:04:41 -050048#define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030049#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666
50#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
51#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
52
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030053/*
Vladimir Zapolskiy936c2002015-12-19 23:41:23 +020054 * USB
55 */
Vladimir Zapolskiy936c2002015-12-19 23:41:23 +020056#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
Vladimir Zapolskiy936c2002015-12-19 23:41:23 +020057
58/*
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000059 * U-Boot General Configurations
60 */
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000061
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030062/*
63 * Pass open firmware flat tree
64 */
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030065
66/*
67 * Environment
68 */
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030069
Tom Rinic9edebe2022-12-04 10:03:50 -050070#define CFG_EXTRA_ENV_SETTINGS \
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030071 "ethaddr=00:01:90:00:C0:81\0" \
72 "dtbaddr=0x81000000\0" \
73 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
74 "tftpdir=vladimir/oe/devkit3250\0" \
75 "userargs=oops=panic\0"
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000076
77/*
78 * U-Boot Commands
79 */
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000080
Simon Glass72cc5382022-10-20 18:22:39 -060081/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */
Tom Rinib4213492022-11-12 17:36:51 -050082#define CFG_SYS_NAND_U_BOOT_SIZE 0x60000
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +030083
Tom Rinib4213492022-11-12 17:36:51 -050084#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
85#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +030086
87/* See common/spl/spl.c spl_set_header_raw_uboot() */
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +030088
89/*
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000090 * Include SoC specific configuration
91 */
92#include <asm/arch/config.h>
93
94#endif /* __CONFIG_DEVKIT3250_H__*/