| Ralph Siemsen | 4ceb0d3 | 2023-05-12 21:36:53 -0400 | [diff] [blame] | 1 | if RAM || SPL_RAM |
| 2 | |||||
| 3 | config CADENCE_DDR_CTRL | ||||
| 4 | bool "Enable Cadence DDR controller" | ||||
| 5 | depends on DM | ||||
| 6 | help | ||||
| 7 | Enable support for Cadence DDR controller, as found on | ||||
| 8 | the Renesas RZ/N1 SoC. This controller has a large number | ||||
| 9 | of registers which need to be programmed, mostly using values | ||||
| 10 | obtained from Denali SOMA files via a TCL script. | ||||
| 11 | |||||
| 12 | endif | ||||