Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/mtd/nand-controller.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: NAND Controller Common Properties |
| 8 | |
| 9 | maintainers: |
| 10 | - Miquel Raynal <miquel.raynal@bootlin.com> |
| 11 | - Richard Weinberger <richard@nod.at> |
| 12 | |
| 13 | description: | |
| 14 | The NAND controller should be represented with its own DT node, and |
| 15 | all NAND chips attached to this controller should be defined as |
| 16 | children nodes of the NAND controller. This representation should be |
| 17 | enforced even for simple controllers supporting only one chip. |
| 18 | |
| 19 | properties: |
| 20 | $nodename: |
| 21 | pattern: "^nand-controller(@.*)?" |
| 22 | |
| 23 | "#address-cells": |
| 24 | const: 1 |
| 25 | |
| 26 | "#size-cells": |
| 27 | const: 0 |
| 28 | |
| 29 | ranges: true |
| 30 | |
| 31 | cs-gpios: |
| 32 | description: |
| 33 | Array of chip-select available to the controller. The first |
| 34 | entries are a 1:1 mapping of the available chip-select on the |
| 35 | NAND controller (even if they are not used). As many additional |
| 36 | chip-select as needed may follow and should be phandles of GPIO |
| 37 | lines. 'reg' entries of the NAND chip subnodes become indexes of |
| 38 | this array when this property is present. |
| 39 | minItems: 1 |
| 40 | maxItems: 8 |
| 41 | |
| 42 | patternProperties: |
| 43 | "^nand@[a-f0-9]$": |
| 44 | type: object |
| 45 | $ref: raw-nand-chip.yaml# |
| 46 | |
| 47 | required: |
| 48 | - "#address-cells" |
| 49 | - "#size-cells" |
| 50 | |
| 51 | # This is a generic file other binding inherit from and extend |
| 52 | additionalProperties: true |
| 53 | |
| 54 | examples: |
| 55 | - | |
| 56 | nand-controller { |
| 57 | #address-cells = <1>; |
| 58 | #size-cells = <0>; |
| 59 | cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */ |
| 60 | |
| 61 | /* controller specific properties */ |
| 62 | |
| 63 | nand@0 { |
| 64 | reg = <0>; /* Native CS */ |
| 65 | /* NAND chip specific properties */ |
| 66 | }; |
| 67 | |
| 68 | nand@1 { |
| 69 | reg = <1>; /* GPIO CS */ |
| 70 | }; |
| 71 | }; |