dts/upstream/Bindings/clock/starfive,jh7100-audclk.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7100 Audio Clock Generator

maintainers:
  - Emil Renner Berthing <kernel@esmil.dk>

properties:
  compatible:
    const: starfive,jh7100-audclk

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Audio source clock
      - description: External 12.288MHz clock
      - description: Domain 7 AHB bus clock

  clock-names:
    items:
      - const: audio_src
      - const: audio_12288
      - const: dom7ahb_bus

  '#clock-cells':
    const: 1
    description:
      See <dt-bindings/clock/starfive-jh7100-audio.h> for valid indices.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/starfive-jh7100.h>

    clock-controller@10480000 {
            compatible = "starfive,jh7100-audclk";
            reg = <0x10480000 0x10000>;
            clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
                     <&clkgen JH7100_CLK_AUDIO_12288>,
                     <&clkgen JH7100_CLK_DOM7AHB_BUS>;
            clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
            #clock-cells = <1>;
    };