| maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 Google Inc. | ||||
| 3 | * | ||||
| 4 | * SPDX-License-Identifier: GPL-2.0+ | ||||
| 5 | */ | ||||
| 6 | |||||
| 7 | /* Core Clocks */ | ||||
| 8 | #define PLL_HPLL 1 | ||||
| 9 | #define PLL_DPLL 2 | ||||
| 10 | #define PLL_D2PLL 3 | ||||
| 11 | #define PLL_MPLL 4 | ||||
| 12 | #define ARMCLK 5 | ||||
| 13 | |||||
| 14 | |||||
| 15 | /* Bus Clocks, derived from core clocks */ | ||||
| 16 | #define BCLK_PCLK 101 | ||||
| 17 | #define BCLK_LHCLK 102 | ||||
| 18 | #define BCLK_MACCLK 103 | ||||
| 19 | #define BCLK_SDCLK 104 | ||||
| 20 | #define BCLK_ARMCLK 105 | ||||
| 21 | |||||
| 22 | #define MCLK_DDR 201 | ||||
| 23 | |||||
| 24 | /* Special clocks */ | ||||
| 25 | #define PCLK_UART1 501 | ||||
| 26 | #define PCLK_UART2 502 | ||||
| 27 | #define PCLK_UART3 503 | ||||
| 28 | #define PCLK_UART4 504 | ||||
| 29 | #define PCLK_UART5 505 | ||||
| maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame^] | 30 | #define PCLK_MAC1 506 |
| 31 | #define PCLK_MAC2 507 | ||||