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git01.mediatek.com / filogic / uboot / 1487903a628b65cff97b18471b626f209f40985a / . / arch / arm / mach-rmobile / pfc-r8a7790.h
blob: e911be4039dcd7f1684e434beb7301ca8f47e777 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Nobuhiro Iwamatsuc6ccb472013-11-21 17:06:45 +0900[diff] [blame]2/*
3 * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
4 *
5 * Copyright (C) 2013 Renesas Electronics Corporation
Nobuhiro Iwamatsuc6ccb472013-11-21 17:06:45 +0900[diff] [blame]6 */
7
8#ifndef __PFC_R8A7790_H__
9#define __PFC_R8A7790_H__
10
11#include <sh_pfc.h>
12#include <asm/gpio.h>
13
14#define CPU_32_PORT(fn, pfx, sfx) \
15 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
16 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
17 PORT_1(fn, pfx##31, sfx)
18
19#define CPU_32_PORT2(fn, pfx, sfx) \
20 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
21 PORT_10(fn, pfx##2, sfx)
22
23#if defined(CONFIG_R8A7790)
24#define CPU_32_PORT1(fn, pfx, sfx) \
25 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
26 PORT_10(fn, pfx##2, sfx) \
27/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
28#define CPU_ALL_PORT(fn, pfx, sfx) \
29 CPU_32_PORT(fn, pfx##_0_, sfx), \
30 CPU_32_PORT1(fn, pfx##_1_, sfx), \
31 CPU_32_PORT2(fn, pfx##_2_, sfx), \
32 CPU_32_PORT(fn, pfx##_3_, sfx), \
33 CPU_32_PORT(fn, pfx##_4_, sfx), \
34 CPU_32_PORT(fn, pfx##_5_, sfx)
35
36#elif defined(CONFIG_R8A7791)
37#define CPU_32_PORT1(fn, pfx, sfx) \
38 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
39 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
40 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
41 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
42
43/*
44 * GP_0_0_DATA -> GP_7_25_DATA
45 * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
46 * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
47 */
48#define CPU_ALL_PORT(fn, pfx, sfx) \
49 CPU_32_PORT(fn, pfx##_0_, sfx), \
50 CPU_32_PORT1(fn, pfx##_1_, sfx), \
51 CPU_32_PORT(fn, pfx##_2_, sfx), \
52 CPU_32_PORT(fn, pfx##_3_, sfx), \
53 CPU_32_PORT(fn, pfx##_4_, sfx), \
54 CPU_32_PORT(fn, pfx##_5_, sfx), \
55 CPU_32_PORT(fn, pfx##_6_, sfx), \
56 CPU_32_PORT1(fn, pfx##_7_, sfx)
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900[diff] [blame]57
58#elif defined(CONFIG_R8A7792)
59/*
60 * GP_0_0_DATA -> GP_11_29_DATA
61 * (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31]
62 * GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31])
63 */
64#define CPU_32_PORT0_28(fn, pfx, sfx) \
65 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
66 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
67 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
68 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
69 PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx), \
70 PORT_1(fn, pfx##28, sfx)
71
72#define CPU_32_PORT0_22(fn, pfx, sfx) \
73 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
74 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
75 PORT_1(fn, pfx##22, sfx)
76
77#define CPU_32_PORT0_27(fn, pfx, sfx) \
78 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
79 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
80 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
81 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
82 PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
83
84#define CPU_32_PORT0_16(fn, pfx, sfx) \
85 PORT_10(fn, pfx, sfx), \
86 PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \
87 PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \
88 PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \
89 PORT_1(fn, pfx##16, sfx)
90
91#define CPU_ALL_PORT(fn, pfx, sfx) \
92 CPU_32_PORT0_28(fn, pfx##_0_, sfx), \
93 CPU_32_PORT0_22(fn, pfx##_1_, sfx), \
94 CPU_32_PORT(fn, pfx##_2_, sfx), \
95 CPU_32_PORT0_27(fn, pfx##_3_, sfx), \
96 CPU_32_PORT0_16(fn, pfx##_4_, sfx), \
97 CPU_32_PORT0_16(fn, pfx##_5_, sfx), \
98 CPU_32_PORT0_16(fn, pfx##_6_, sfx), \
99 CPU_32_PORT0_16(fn, pfx##_7_, sfx), \
100 CPU_32_PORT0_16(fn, pfx##_8_, sfx), \
101 CPU_32_PORT0_16(fn, pfx##_9_, sfx), \
102 CPU_32_PORT(fn, pfx##_10_, sfx), \
103 CPU_32_PORT2(fn, pfx##_11_, sfx)
104
Nobuhiro Iwamatsuc6ccb472013-11-21 17:06:45 +0900[diff] [blame]105#else
106#error "NO support"
107#endif
108
109#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
110#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
111 GP##pfx##_IN, GP##pfx##_OUT)
112
113#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
114#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
115
116#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
117#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
118#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
119
120#define PORT_10_REV(fn, pfx, sfx) \
121 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
122 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
123 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
124 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
125 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
126
127#define CPU_32_PORT_REV(fn, pfx, sfx) \
128 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
129 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
130 PORT_10_REV(fn, pfx, sfx)
131
132#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
133#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
134
135#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
136#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
137 FN_##ipsr, FN_##fn)
138
139#endif /* __PFC_R8A7790_H__ */