Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2014 Freescale Semiconductor, Inc. |
Rajesh Bhagat | aec3801 | 2021-11-09 16:30:38 +0530 | [diff] [blame] | 4 | * Copyright 2020-2021 NXP |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * T1024/T1023 RDB board configuration file |
| 9 | */ |
| 10 | |
| 11 | #ifndef __T1024RDB_H |
| 12 | #define __T1024RDB_H |
| 13 | |
Simon Glass | fb64e36 | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 14 | #include <linux/stringify.h> |
| 15 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 16 | /* High Level Configuration Options */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 17 | |
Tom Rini | 0a2bac7 | 2022-11-16 13:10:29 -0500 | [diff] [blame] | 18 | #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 19 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 20 | #ifdef CONFIG_RAMBOOT_PBL |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 21 | #define RESET_VECTOR_OFFSET 0x27FFC |
| 22 | #define BOOT_PAGE_OFFSET 0x27000 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 23 | |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 24 | #ifdef CONFIG_MTD_RAW_NAND |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 25 | #define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
| 26 | #define CFG_SYS_NAND_U_BOOT_DST 0x30000000 |
| 27 | #define CFG_SYS_NAND_U_BOOT_START 0x30000000 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 28 | #endif |
| 29 | |
| 30 | #ifdef CONFIG_SPIFLASH |
tang yuantian | 8dc02f3 | 2014-12-17 15:42:54 +0800 | [diff] [blame] | 31 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 32 | #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
| 33 | #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) |
| 34 | #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) |
| 35 | #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 36 | #endif |
| 37 | |
| 38 | #ifdef CONFIG_SDCARD |
tang yuantian | 8dc02f3 | 2014-12-17 15:42:54 +0800 | [diff] [blame] | 39 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 40 | #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| 41 | #define CFG_SYS_MMC_U_BOOT_DST (0x30000000) |
| 42 | #define CFG_SYS_MMC_U_BOOT_START (0x30000000) |
| 43 | #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 44 | #endif |
| 45 | |
| 46 | #endif /* CONFIG_RAMBOOT_PBL */ |
| 47 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 48 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 49 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 50 | #endif |
| 51 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 52 | /* |
| 53 | * for slave u-boot IMAGE instored in master memory space, |
| 54 | * PHYS must be aligned based on the SIZE |
| 55 | */ |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 56 | #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull |
| 57 | #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 58 | #ifdef CONFIG_PHYS_64BIT |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 59 | #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
| 60 | #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 61 | #else |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 62 | #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 |
| 63 | #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 64 | #endif |
| 65 | /* |
| 66 | * for slave UCODE and ENV instored in master memory space, |
| 67 | * PHYS must be aligned based on the SIZE |
| 68 | */ |
| 69 | #ifdef CONFIG_PHYS_64BIT |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 70 | #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
| 71 | #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 72 | #else |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 73 | #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 |
| 74 | #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 75 | #endif |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 76 | #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 77 | /* slave core release by master*/ |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 78 | #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 |
| 79 | #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 80 | |
| 81 | /* PCIe Boot - Slave */ |
| 82 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 83 | #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 |
| 84 | #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ |
| 85 | (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 86 | /* Set 1M boot space for PCIe boot */ |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 87 | #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) |
| 88 | #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ |
| 89 | (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 90 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 91 | #endif |
| 92 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 93 | /* |
| 94 | * These can be toggled for performance analysis, otherwise use default. |
| 95 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 96 | #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 97 | #ifdef CONFIG_DDR_ECC |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 98 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 99 | #endif |
| 100 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 101 | /* |
| 102 | * Config the L3 Cache as L3 SRAM |
| 103 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 104 | #define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 |
Tom Rini | 5cd7ece | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 105 | #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 106 | |
| 107 | #ifdef CONFIG_PHYS_64BIT |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 108 | #define CFG_SYS_DCSRBAR 0xf0000000 |
| 109 | #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 110 | #endif |
| 111 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 112 | /* |
| 113 | * DDR Setup |
| 114 | */ |
| 115 | #define CONFIG_VERY_BIG_RAM |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 116 | #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 117 | #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE |
York Sun | f9a0363 | 2016-12-28 08:43:34 -0800 | [diff] [blame] | 118 | #if defined(CONFIG_TARGET_T1024RDB) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 119 | #define SPD_EEPROM_ADDRESS 0x51 |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 120 | #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
York Sun | 940ee4a | 2016-12-28 08:43:33 -0800 | [diff] [blame] | 121 | #elif defined(CONFIG_TARGET_T1023RDB) |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 122 | #define CFG_SYS_SDRAM_SIZE 2048 |
Shengzhou Liu | 00d7e5b | 2015-03-27 15:48:34 +0800 | [diff] [blame] | 123 | #endif |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 124 | |
| 125 | /* |
| 126 | * IFC Definitions |
| 127 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 128 | #define CFG_SYS_FLASH_BASE 0xe8000000 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 129 | #ifdef CONFIG_PHYS_64BIT |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 130 | #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 131 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 132 | #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 133 | #endif |
| 134 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 135 | #define CFG_SYS_NOR0_CSPR_EXT (0xf) |
| 136 | #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 137 | CSPR_PORT_SIZE_16 | \ |
| 138 | CSPR_MSEL_NOR | \ |
| 139 | CSPR_V) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 140 | #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 141 | |
| 142 | /* NOR Flash Timing Params */ |
York Sun | f9a0363 | 2016-12-28 08:43:34 -0800 | [diff] [blame] | 143 | #if defined(CONFIG_TARGET_T1024RDB) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 144 | #define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
York Sun | 940ee4a | 2016-12-28 08:43:33 -0800 | [diff] [blame] | 145 | #elif defined(CONFIG_TARGET_T1023RDB) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 146 | #define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ |
Shengzhou Liu | 00d7e5b | 2015-03-27 15:48:34 +0800 | [diff] [blame] | 147 | CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) |
| 148 | #endif |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 149 | #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 150 | FTIM0_NOR_TEADC(0x5) | \ |
| 151 | FTIM0_NOR_TEAHC(0x5)) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 152 | #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 153 | FTIM1_NOR_TRAD_NOR(0x1A) |\ |
| 154 | FTIM1_NOR_TSEQRAD_NOR(0x13)) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 155 | #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 156 | FTIM2_NOR_TCH(0x4) | \ |
| 157 | FTIM2_NOR_TWPH(0x0E) | \ |
| 158 | FTIM2_NOR_TWP(0x1c)) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 159 | #define CFG_SYS_NOR_FTIM3 0x0 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 160 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 161 | #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 162 | |
York Sun | f9a0363 | 2016-12-28 08:43:34 -0800 | [diff] [blame] | 163 | #ifdef CONFIG_TARGET_T1024RDB |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 164 | /* CPLD on IFC */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 165 | #define CFG_SYS_CPLD_BASE 0xffdf0000 |
| 166 | #define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) |
| 167 | #define CFG_SYS_CSPR2_EXT (0xf) |
| 168 | #define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 169 | | CSPR_PORT_SIZE_8 \ |
| 170 | | CSPR_MSEL_GPCM \ |
| 171 | | CSPR_V) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 172 | #define CFG_SYS_AMASK2 IFC_AMASK(64*1024) |
| 173 | #define CFG_SYS_CSOR2 0x0 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 174 | |
| 175 | /* CPLD Timing parameters for IFC CS2 */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 176 | #define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 177 | FTIM0_GPCM_TEADC(0x0e) | \ |
| 178 | FTIM0_GPCM_TEAHC(0x0e)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 179 | #define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 180 | FTIM1_GPCM_TRAD(0x1f)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 181 | #define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 182 | FTIM2_GPCM_TCH(0x8) | \ |
| 183 | FTIM2_GPCM_TWP(0x1f)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 184 | #define CFG_SYS_CS2_FTIM3 0x0 |
Shengzhou Liu | 00d7e5b | 2015-03-27 15:48:34 +0800 | [diff] [blame] | 185 | #endif |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 186 | |
| 187 | /* NAND Flash on IFC */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 188 | #define CFG_SYS_NAND_BASE 0xff800000 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 189 | #ifdef CONFIG_PHYS_64BIT |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 190 | #define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 191 | #else |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 192 | #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 193 | #endif |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 194 | #define CFG_SYS_NAND_CSPR_EXT (0xf) |
| 195 | #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 196 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ |
| 197 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ |
| 198 | | CSPR_V) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 199 | #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 200 | |
York Sun | f9a0363 | 2016-12-28 08:43:34 -0800 | [diff] [blame] | 201 | #if defined(CONFIG_TARGET_T1024RDB) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 202 | #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 203 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 204 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 205 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ |
| 206 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ |
| 207 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ |
| 208 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
York Sun | 940ee4a | 2016-12-28 08:43:33 -0800 | [diff] [blame] | 209 | #elif defined(CONFIG_TARGET_T1023RDB) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 210 | #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
Jaiprakash Singh | c4e609f | 2015-05-22 15:21:07 +0530 | [diff] [blame] | 211 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 212 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
Shengzhou Liu | 00d7e5b | 2015-03-27 15:48:34 +0800 | [diff] [blame] | 213 | | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ |
| 214 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ |
| 215 | | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ |
| 216 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
Shengzhou Liu | 00d7e5b | 2015-03-27 15:48:34 +0800 | [diff] [blame] | 217 | #endif |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 218 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 219 | /* ONFI NAND Flash mode0 Timing Params */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 220 | #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 221 | FTIM0_NAND_TWP(0x18) | \ |
| 222 | FTIM0_NAND_TWCHT(0x07) | \ |
| 223 | FTIM0_NAND_TWH(0x0a)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 224 | #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 225 | FTIM1_NAND_TWBE(0x39) | \ |
| 226 | FTIM1_NAND_TRR(0x0e) | \ |
| 227 | FTIM1_NAND_TRP(0x18)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 228 | #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 229 | FTIM2_NAND_TREH(0x0a) | \ |
| 230 | FTIM2_NAND_TWHRE(0x1e)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 231 | #define CFG_SYS_NAND_FTIM3 0x0 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 232 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 233 | #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 234 | |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 235 | #if defined(CONFIG_MTD_RAW_NAND) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 236 | #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT |
| 237 | #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR |
| 238 | #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK |
| 239 | #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR |
| 240 | #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 |
| 241 | #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 |
| 242 | #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 |
| 243 | #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 |
| 244 | #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT |
| 245 | #define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR |
| 246 | #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK |
| 247 | #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR |
| 248 | #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 |
| 249 | #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 |
| 250 | #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 |
| 251 | #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 252 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 253 | #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT |
| 254 | #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR |
| 255 | #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK |
| 256 | #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR |
| 257 | #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 |
| 258 | #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 |
| 259 | #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 |
| 260 | #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 |
| 261 | #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT |
| 262 | #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR |
| 263 | #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK |
| 264 | #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR |
| 265 | #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 |
| 266 | #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 |
| 267 | #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 |
| 268 | #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 269 | #endif |
| 270 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 271 | /* define to use L1 as initial stack */ |
| 272 | #define CONFIG_L1_INIT_RAM |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 273 | #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 274 | #ifdef CONFIG_PHYS_64BIT |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 275 | #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
| 276 | #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 277 | /* The assembler doesn't like typecast */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 278 | #define CFG_SYS_INIT_RAM_ADDR_PHYS \ |
| 279 | ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ |
| 280 | CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 281 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 282 | #define CFG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ |
| 283 | #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 |
| 284 | #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 285 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 286 | #define CFG_SYS_INIT_RAM_SIZE 0x00004000 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 287 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 288 | #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 289 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 290 | /* Serial Port */ |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 291 | #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 292 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 293 | #define CFG_SYS_BAUDRATE_TABLE \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 294 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 295 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 296 | #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) |
| 297 | #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) |
| 298 | #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) |
| 299 | #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 300 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 301 | /* I2C */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 302 | |
Shengzhou Liu | 0a19789 | 2015-06-17 16:37:01 +0800 | [diff] [blame] | 303 | #define I2C_PCA6408_BUS_NUM 1 |
| 304 | #define I2C_PCA6408_ADDR 0x20 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 305 | |
| 306 | /* I2C bus multiplexer */ |
| 307 | #define I2C_MUX_CH_DEFAULT 0x8 |
| 308 | |
| 309 | /* |
| 310 | * RTC configuration |
| 311 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 312 | #define CFG_SYS_I2C_RTC_ADDR 0x68 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 313 | |
| 314 | /* |
| 315 | * eSPI - Enhanced SPI |
| 316 | */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 317 | |
| 318 | /* |
| 319 | * General PCIe |
| 320 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 321 | */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 322 | |
| 323 | #ifdef CONFIG_PCI |
| 324 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
| 325 | #ifdef CONFIG_PCIE1 |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 326 | #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 327 | #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 328 | #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 |
| 329 | #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 330 | #endif |
| 331 | |
| 332 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ |
| 333 | #ifdef CONFIG_PCIE2 |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 334 | #define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 |
| 335 | #define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull |
| 336 | #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 |
| 337 | #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 338 | #endif |
| 339 | |
| 340 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
| 341 | #ifdef CONFIG_PCIE3 |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 342 | #define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
| 343 | #define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 344 | #endif |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 345 | #endif /* CONFIG_PCI */ |
| 346 | |
| 347 | /* |
| 348 | * USB |
| 349 | */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 350 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 351 | /* |
| 352 | * SDHC |
| 353 | */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 354 | #ifdef CONFIG_MMC |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 355 | #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 356 | #endif |
| 357 | |
| 358 | /* Qman/Bman */ |
| 359 | #ifndef CONFIG_NOBQFMAN |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 360 | #define CFG_SYS_BMAN_NUM_PORTALS 10 |
| 361 | #define CFG_SYS_BMAN_MEM_BASE 0xf4000000 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 362 | #ifdef CONFIG_PHYS_64BIT |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 363 | #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 364 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 365 | #define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 366 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 367 | #define CFG_SYS_BMAN_MEM_SIZE 0x02000000 |
| 368 | #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 369 | #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 |
| 370 | #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE |
| 371 | #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) |
| 372 | #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ |
| 373 | CFG_SYS_BMAN_CENA_SIZE) |
| 374 | #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) |
| 375 | #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 |
| 376 | #define CFG_SYS_QMAN_NUM_PORTALS 10 |
| 377 | #define CFG_SYS_QMAN_MEM_BASE 0xf6000000 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 378 | #ifdef CONFIG_PHYS_64BIT |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 379 | #define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 380 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 381 | #define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 382 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 383 | #define CFG_SYS_QMAN_MEM_SIZE 0x02000000 |
| 384 | #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 |
| 385 | #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) |
| 386 | #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ |
| 387 | CFG_SYS_QMAN_CENA_SIZE) |
| 388 | #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) |
| 389 | #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 |
| 390 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 391 | #endif /* CONFIG_NOBQFMAN */ |
| 392 | |
| 393 | #ifdef CONFIG_SYS_DPAA_FMAN |
York Sun | f9a0363 | 2016-12-28 08:43:34 -0800 | [diff] [blame] | 394 | #if defined(CONFIG_TARGET_T1024RDB) |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 395 | #define RGMII_PHY1_ADDR 0x2 |
| 396 | #define RGMII_PHY2_ADDR 0x6 |
Shengzhou Liu | 00d7e5b | 2015-03-27 15:48:34 +0800 | [diff] [blame] | 397 | #define SGMII_AQR_PHY_ADDR 0x2 |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 398 | #define FM1_10GEC1_PHY_ADDR 0x1 |
York Sun | 940ee4a | 2016-12-28 08:43:33 -0800 | [diff] [blame] | 399 | #elif defined(CONFIG_TARGET_T1023RDB) |
Shengzhou Liu | 00d7e5b | 2015-03-27 15:48:34 +0800 | [diff] [blame] | 400 | #define RGMII_PHY1_ADDR 0x1 |
| 401 | #define SGMII_RTK_PHY_ADDR 0x3 |
| 402 | #define SGMII_AQR_PHY_ADDR 0x2 |
| 403 | #endif |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 404 | #endif |
| 405 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 406 | /* |
| 407 | * Dynamic MTD Partition support with mtdparts |
| 408 | */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 409 | |
| 410 | /* |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 411 | * Miscellaneous configurable options |
| 412 | */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 413 | |
| 414 | /* |
| 415 | * For booting Linux, the board info and command line data |
| 416 | * have to be in the first 64 MB of memory, since this is |
| 417 | * the maximum mapped by the Linux kernel during initialization. |
| 418 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 419 | #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 420 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 421 | /* |
| 422 | * Environment Configuration |
| 423 | */ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 424 | #define __USB_PHY_TYPE utmi |
| 425 | |
York Sun | 7d29dd6 | 2016-11-18 13:01:34 -0800 | [diff] [blame] | 426 | #ifdef CONFIG_ARCH_T1024 |
Tom Rini | 272eb5b | 2022-03-21 21:33:32 -0400 | [diff] [blame] | 427 | #define ARCH_EXTRA_ENV_SETTINGS \ |
| 428 | "bank_intlv=cs0_cs1\0" \ |
| 429 | "ramdiskfile=t1024rdb/ramdisk.uboot\0" \ |
| 430 | "fdtfile=t1024rdb/t1024rdb.dtb\0" |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 431 | #else |
Tom Rini | 272eb5b | 2022-03-21 21:33:32 -0400 | [diff] [blame] | 432 | #define ARCH_EXTRA_ENV_SETTINGS \ |
| 433 | "bank_intlv=null\0" \ |
| 434 | "ramdiskfile=t1023rdb/ramdisk.uboot\0" \ |
| 435 | "fdtfile=t1023rdb/t1023rdb.dtb\0" |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 436 | #endif |
| 437 | |
| 438 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Tom Rini | 272eb5b | 2022-03-21 21:33:32 -0400 | [diff] [blame] | 439 | ARCH_EXTRA_ENV_SETTINGS \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 440 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 441 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ |
Tom Rini | 1479a83 | 2022-12-02 16:42:27 -0500 | [diff] [blame^] | 442 | "uboot=" CONFIG_UBOOTPATH "\0" \ |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 443 | "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 444 | "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ |
| 445 | "netdev=eth0\0" \ |
| 446 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
| 447 | "protect off $ubootaddr +$filesize && " \ |
| 448 | "erase $ubootaddr +$filesize && " \ |
| 449 | "cp.b $loadaddr $ubootaddr $filesize && " \ |
| 450 | "protect on $ubootaddr +$filesize && " \ |
| 451 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ |
| 452 | "consoledev=ttyS0\0" \ |
| 453 | "ramdiskaddr=2000000\0" \ |
Scott Wood | b7f4b85 | 2016-07-19 17:52:06 -0500 | [diff] [blame] | 454 | "fdtaddr=1e00000\0" \ |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 455 | "bdev=sda3\0" |
| 456 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 457 | #include <asm/fsl_secure_boot.h> |
Aneesh Bansal | 962021a | 2016-01-22 16:37:22 +0530 | [diff] [blame] | 458 | |
Shengzhou Liu | 4991240 | 2014-11-24 17:11:56 +0800 | [diff] [blame] | 459 | #endif /* __T1024RDB_H */ |