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git01.mediatek.com / filogic / uboot / 78cefc083c5efdcb3734b896aea78d6e38b3b1cd / . / arch / arm / dts / exynos54xx.dtsi
blob: 7892345e2ee277ce0da18476ad3077c494458478 [file] [log] [blame]
Akshay Saraswatfdd9df32014-06-18 17:53:58 +0530[diff] [blame]1/*
2 * (C) Copyright 2013 SAMSUNG Electronics
3 * SAMSUNG EXYNOS5420 SoC device tree source
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
Simon Glass78cefc02014-10-20 19:48:29 -0600[diff] [blame^]8#include "exynos5.dtsi"
Akshay Saraswatfdd9df32014-06-18 17:53:58 +0530[diff] [blame]9
10/ {
11 config {
12 machine-arch-id = <4151>;
13 };
14
15 aliases {
16 i2c0 = "/i2c@12c60000";
17 i2c1 = "/i2c@12c70000";
18 i2c2 = "/i2c@12c80000";
19 i2c3 = "/i2c@12c90000";
20 i2c4 = "/i2c@12ca0000";
21 i2c5 = "/i2c@12cb0000";
22 i2c6 = "/i2c@12cc0000";
23 i2c7 = "/i2c@12cd0000";
24 i2c8 = "/i2c@12e00000";
25 i2c9 = "/i2c@12e10000";
26 i2c10 = "/i2c@12e20000";
27 spi0 = "/spi@12d20000";
28 spi1 = "/spi@12d30000";
29 spi2 = "/spi@12d40000";
30 spi3 = "/spi@131a0000";
31 spi4 = "/spi@131b0000";
32 mmc0 = "/mmc@12200000";
33 mmc1 = "/mmc@12210000";
34 mmc2 = "/mmc@12220000";
35 xhci0 = "/xhci@12000000";
36 xhci1 = "/xhci@12400000";
37 };
38
39 i2c@12ca0000 {
40 #address-cells = <1>;
41 #size-cells = <0>;
42 compatible = "samsung,exynos5-hsi2c";
43 reg = <0x12CA0000 0x100>;
44 interrupts = <0 60 0>;
45 };
46
47 i2c@12cb0000 {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 compatible = "samsung,exynos5-hsi2c";
51 reg = <0x12CB0000 0x100>;
52 interrupts = <0 61 0>;
53 };
54
55 i2c@12cc0000 {
56 #address-cells = <1>;
57 #size-cells = <0>;
58 compatible = "samsung,exynos5-hsi2c";
59 reg = <0x12CC0000 0x100>;
60 interrupts = <0 62 0>;
61 };
62
63 i2c@12cd0000 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 compatible = "samsung,exynos5-hsi2c";
67 reg = <0x12CD0000 0x100>;
68 interrupts = <0 63 0>;
69 };
70
71 i2c@12e00000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 compatible = "samsung,exynos5-hsi2c";
75 reg = <0x12E00000 0x100>;
76 interrupts = <0 87 0>;
77 };
78
79 i2c@12e10000 {
80 #address-cells = <1>;
81 #size-cells = <0>;
82 compatible = "samsung,exynos5-hsi2c";
83 reg = <0x12E10000 0x100>;
84 interrupts = <0 88 0>;
85 };
86
87 i2c@12e20000 {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 compatible = "samsung,exynos5-hsi2c";
91 reg = <0x12E20000 0x100>;
92 interrupts = <0 203 0>;
93 };
94
95 mmc@12200000 {
96 samsung,bus-width = <8>;
97 samsung,timing = <1 3 3>;
98 samsung,removable = <0>;
99 samsung,pre-init;
100 };
101
102 mmc@12210000 {
103 status = "disabled";
104 };
105
106 mmc@12220000 {
107 samsung,bus-width = <4>;
108 samsung,timing = <1 2 3>;
109 samsung,removable = <1>;
110 };
111
112 mmc@12230000 {
113 status = "disabled";
114 };
115
Ajay Kumare24c5022014-09-05 16:53:33 +0530[diff] [blame]116 fimdm0_sysmmu@0x14640000 {
117 compatible = "samsung,sysmmu-v3.3";
118 reg = <0x14640000 0x100>;
119 };
120
121 fimdm1_sysmmu@0x14680000 {
122 compatible = "samsung,sysmmu-v3.3";
123 reg = <0x14680000 0x100>;
124 };
125
Akshay Saraswatfdd9df32014-06-18 17:53:58 +0530[diff] [blame]126 fimd@14400000 {
127 /* sysmmu is not used in U-Boot */
128 samsung,disable-sysmmu;
129 };
130
131 dp@145b0000 {
132 samsung,lt-status = <0>;
133
134 samsung,master-mode = <0>;
135 samsung,bist-mode = <0>;
136 samsung,bist-pattern = <0>;
137 samsung,h-sync-polarity = <0>;
138 samsung,v-sync-polarity = <0>;
139 samsung,interlaced = <0>;
140 samsung,color-space = <0>;
141 samsung,dynamic-range = <0>;
142 samsung,ycbcr-coeff = <0>;
143 samsung,color-depth = <1>;
144 };
145
146 dmc {
147 mem-type = "ddr3";
148 };
149
150 xhci1: xhci@12400000 {
151 compatible = "samsung,exynos5250-xhci";
152 reg = <0x12400000 0x10000>;
153 #address-cells = <1>;
154 #size-cells = <1>;
155
156 phy {
157 compatible = "samsung,exynos5250-usb3-phy";
158 reg = <0x12500000 0x100>;
159 };
160 };
161};