Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_K3=y |
Tom Rini | e25a03a | 2021-11-01 12:19:22 +0000 | [diff] [blame] | 3 | CONFIG_SYS_MALLOC_LEN=0x2000000 |
| 4 | CONFIG_SYS_MALLOC_F_LEN=0x55000 |
Simon Glass | 035939e | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 5 | CONFIG_SPL_GPIO=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 6 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 7 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
Tom Rini | 2e262c4 | 2020-08-10 15:31:07 -0400 | [diff] [blame] | 8 | CONFIG_NR_DRAM_BANKS=2 |
Andrew Davis | 1be5e97 | 2022-07-15 10:25:27 -0500 | [diff] [blame] | 9 | CONFIG_SOC_K3_AM654=y |
Andreas Dannenberg | 1a9dbdc | 2019-08-15 15:55:31 -0500 | [diff] [blame] | 10 | CONFIG_K3_EARLY_CONS=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 11 | CONFIG_TARGET_AM654_R5_EVM=y |
Tom Rini | 9924ca1 | 2023-02-17 09:58:06 -0500 | [diff] [blame] | 12 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 13 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c7effc |
Tom Rini | f6e6e1a | 2020-01-22 13:38:00 -0500 | [diff] [blame] | 14 | CONFIG_ENV_SIZE=0x20000 |
| 15 | CONFIG_DM_GPIO=y |
Tom Rini | 6c75e63 | 2020-06-16 19:06:29 -0400 | [diff] [blame] | 16 | CONFIG_SPL_DM_SPI=y |
Tom Rini | a20e51f | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 17 | CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" |
Tom Rini | 0332a1a | 2020-07-06 13:54:25 -0400 | [diff] [blame] | 18 | CONFIG_SPL_TEXT_BASE=0x41c00000 |
Tom Rini | 9924ca1 | 2023-02-17 09:58:06 -0500 | [diff] [blame] | 19 | CONFIG_DM_RESET=y |
Simon Glass | b58bfe0 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 20 | CONFIG_SPL_MMC=y |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 21 | CONFIG_SPL_SERIAL=y |
Simon Glass | 284cb9c | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 22 | CONFIG_SPL_DRIVERS_MISC=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 23 | CONFIG_SPL_STACK_R_ADDR=0x82000000 |
Lokesh Vutla | 7ecde56 | 2021-03-09 23:32:45 +0530 | [diff] [blame] | 24 | CONFIG_SPL_SIZE_LIMIT=0x7ec00 |
| 25 | CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 |
Tien Fong Chee | 6fd0a71 | 2019-01-23 14:20:03 +0800 | [diff] [blame] | 26 | CONFIG_SPL_FS_FAT=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 27 | CONFIG_SPL_LIBDISK_SUPPORT=y |
Vignesh Raghavendra | 0242ba2 | 2020-02-04 11:09:56 +0530 | [diff] [blame] | 28 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
Simon Glass | a582047 | 2021-08-08 12:20:14 -0600 | [diff] [blame] | 29 | CONFIG_SPL_SPI=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 30 | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
| 31 | CONFIG_SPL_LOAD_FIT=y |
| 32 | CONFIG_USE_BOOTCOMMAND=y |
| 33 | # CONFIG_DISPLAY_CPUINFO is not set |
Lokesh Vutla | 7ecde56 | 2021-03-09 23:32:45 +0530 | [diff] [blame] | 34 | CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y |
| 35 | CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y |
Tom Rini | abb0f52 | 2022-05-16 17:20:26 -0400 | [diff] [blame] | 36 | CONFIG_SPL_MAX_SIZE=0x58000 |
Tom Rini | 65aa124 | 2022-05-27 10:19:45 -0400 | [diff] [blame] | 37 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 38 | CONFIG_SPL_BSS_START_ADDR=0x41c7effc |
Tom Rini | 0cb89e7 | 2022-05-19 15:09:22 -0400 | [diff] [blame] | 39 | CONFIG_SPL_BSS_MAX_SIZE=0xc00 |
Lokesh Vutla | 7ecde56 | 2021-03-09 23:32:45 +0530 | [diff] [blame] | 40 | CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 41 | CONFIG_SPL_STACK_R=y |
| 42 | CONFIG_SPL_SEPARATE_BSS=y |
Tom Rini | 166e322 | 2022-05-27 12:48:32 -0400 | [diff] [blame] | 43 | CONFIG_SYS_SPL_MALLOC=y |
| 44 | CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y |
| 45 | CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 |
| 46 | CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 |
Andreas Dannenberg | f595cac | 2019-06-04 17:55:51 -0500 | [diff] [blame] | 47 | CONFIG_SPL_EARLY_BSS=y |
Faiz Abbas | c7f3321 | 2019-06-04 17:55:53 -0500 | [diff] [blame] | 48 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y |
| 49 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 |
Vignesh Raghavendra | 0242ba2 | 2020-02-04 11:09:56 +0530 | [diff] [blame] | 50 | CONFIG_SPL_DMA=y |
Simon Glass | bccfc2e | 2021-07-10 21:14:36 -0600 | [diff] [blame] | 51 | CONFIG_SPL_I2C=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 52 | CONFIG_SPL_DM_MAILBOX=y |
Lukasz Majewski | 76f44298 | 2020-06-04 23:11:53 +0800 | [diff] [blame] | 53 | CONFIG_SPL_DM_SPI_FLASH=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 54 | CONFIG_SPL_DM_RESET=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 55 | CONFIG_SPL_POWER_DOMAIN=y |
| 56 | CONFIG_SPL_RAM_SUPPORT=y |
| 57 | CONFIG_SPL_RAM_DEVICE=y |
| 58 | CONFIG_SPL_REMOTEPROC=y |
Vignesh Raghavendra | 0242ba2 | 2020-02-04 11:09:56 +0530 | [diff] [blame] | 59 | # CONFIG_SPL_SPI_FLASH_TINY is not set |
| 60 | CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y |
| 61 | CONFIG_SPL_SPI_LOAD=y |
Tom Rini | e22fa4f | 2021-08-10 15:08:46 -0400 | [diff] [blame] | 62 | CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 63 | CONFIG_SPL_YMODEM_SUPPORT=y |
| 64 | CONFIG_HUSH_PARSER=y |
Tom Rini | ba5c2b0 | 2022-05-11 16:21:06 -0400 | [diff] [blame] | 65 | CONFIG_SYS_MAXARGS=64 |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 66 | CONFIG_CMD_BOOTZ=y |
Tom Rini | f3c2f99 | 2022-06-25 19:29:46 -0400 | [diff] [blame] | 67 | CONFIG_SYS_BOOTM_LEN=0x4000000 |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 68 | CONFIG_CMD_ASKENV=y |
Andrew F. Davis | 43ff952 | 2019-02-01 15:04:56 -0600 | [diff] [blame] | 69 | CONFIG_CMD_GPT=y |
Andreas Dannenberg | cc2b311 | 2019-06-04 18:08:16 -0500 | [diff] [blame] | 70 | CONFIG_CMD_I2C=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 71 | CONFIG_CMD_MMC=y |
| 72 | CONFIG_CMD_REMOTEPROC=y |
| 73 | # CONFIG_CMD_SETEXPR is not set |
| 74 | CONFIG_CMD_TIME=y |
| 75 | CONFIG_CMD_FAT=y |
| 76 | CONFIG_OF_CONTROL=y |
| 77 | CONFIG_SPL_OF_CONTROL=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 78 | CONFIG_SPL_MULTI_DTB_FIT=y |
| 79 | CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y |
Adam Ford | 710966e | 2020-07-03 06:48:56 -0500 | [diff] [blame] | 80 | CONFIG_ENV_OVERWRITE=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 81 | CONFIG_ENV_IS_IN_FAT=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 82 | CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" |
Tom Rini | ca63e71 | 2019-11-12 22:46:36 -0500 | [diff] [blame] | 83 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 84 | CONFIG_SPL_DM=y |
| 85 | CONFIG_SPL_DM_SEQ_ALIAS=y |
Faiz Abbas | 8c10b82 | 2019-06-11 00:43:39 +0530 | [diff] [blame] | 86 | CONFIG_REGMAP=y |
| 87 | CONFIG_SPL_REGMAP=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 88 | CONFIG_SPL_OF_TRANSLATE=y |
| 89 | CONFIG_CLK=y |
| 90 | CONFIG_SPL_CLK=y |
| 91 | CONFIG_CLK_TI_SCI=y |
Vignesh Raghavendra | 0242ba2 | 2020-02-04 11:09:56 +0530 | [diff] [blame] | 92 | CONFIG_DMA_CHANNELS=y |
| 93 | CONFIG_TI_K3_NAVSS_UDMA=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 94 | CONFIG_TI_SCI_PROTOCOL=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 95 | CONFIG_DA8XX_GPIO=y |
Andreas Dannenberg | cc2b311 | 2019-06-04 18:08:16 -0500 | [diff] [blame] | 96 | CONFIG_DM_I2C=y |
| 97 | CONFIG_I2C_SET_DEFAULT_BUS_NUM=y |
| 98 | CONFIG_SYS_I2C_OMAP24XX=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 99 | CONFIG_DM_MAILBOX=y |
| 100 | CONFIG_K3_SEC_PROXY=y |
Tom Rini | fdc7e36 | 2019-11-11 20:04:24 -0500 | [diff] [blame] | 101 | CONFIG_K3_AVS0=y |
Faiz Abbas | 259412b | 2020-02-26 13:44:38 +0530 | [diff] [blame] | 102 | CONFIG_SUPPORT_EMMC_BOOT=y |
Faiz Abbas | a584801 | 2021-02-04 15:11:05 +0530 | [diff] [blame] | 103 | CONFIG_MMC_HS200_SUPPORT=y |
| 104 | CONFIG_SPL_MMC_HS200_SUPPORT=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 105 | CONFIG_MMC_SDHCI=y |
Faiz Abbas | 20e675b | 2019-11-19 14:06:41 +0530 | [diff] [blame] | 106 | CONFIG_SPL_MMC_SDHCI_ADMA=y |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 107 | CONFIG_MMC_SDHCI_AM654=y |
Vignesh Raghavendra | 0242ba2 | 2020-02-04 11:09:56 +0530 | [diff] [blame] | 108 | CONFIG_DM_SPI_FLASH=y |
| 109 | CONFIG_SPI_FLASH_SFDP_SUPPORT=y |
| 110 | CONFIG_SPI_FLASH_STMICRO=y |
| 111 | # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 112 | CONFIG_PINCTRL=y |
| 113 | # CONFIG_PINCTRL_GENERIC is not set |
| 114 | CONFIG_SPL_PINCTRL=y |
| 115 | # CONFIG_SPL_PINCTRL_GENERIC is not set |
| 116 | CONFIG_PINCTRL_SINGLE=y |
| 117 | CONFIG_POWER_DOMAIN=y |
| 118 | CONFIG_TI_SCI_POWER_DOMAIN=y |
| 119 | CONFIG_DM_REGULATOR=y |
| 120 | CONFIG_SPL_DM_REGULATOR=y |
| 121 | CONFIG_DM_REGULATOR_GPIO=y |
| 122 | CONFIG_SPL_DM_REGULATOR_GPIO=y |
Tero Kristo | 5acf501 | 2019-10-24 15:01:01 +0530 | [diff] [blame] | 123 | CONFIG_DM_REGULATOR_TPS62360=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 124 | CONFIG_RAM=y |
| 125 | CONFIG_SPL_RAM=y |
| 126 | CONFIG_K3_SYSTEM_CONTROLLER=y |
Lokesh Vutla | 247418b | 2019-06-07 19:25:59 +0530 | [diff] [blame] | 127 | CONFIG_REMOTEPROC_TI_K3_ARM64=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 128 | CONFIG_RESET_TI_SCI=y |
| 129 | CONFIG_DM_SERIAL=y |
Tom Rini | 8461027 | 2020-07-28 08:46:52 -0400 | [diff] [blame] | 130 | CONFIG_SOC_DEVICE=y |
| 131 | CONFIG_SOC_DEVICE_TI_K3=y |
Vignesh Raghavendra | 0242ba2 | 2020-02-04 11:09:56 +0530 | [diff] [blame] | 132 | CONFIG_SOC_TI=y |
| 133 | CONFIG_SPI=y |
| 134 | CONFIG_DM_SPI=y |
| 135 | CONFIG_CADENCE_QSPI=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 136 | CONFIG_SYSRESET=y |
Kever Yang | 525ea47 | 2019-04-02 20:41:25 +0800 | [diff] [blame] | 137 | CONFIG_SPL_SYSRESET=y |
Lokesh Vutla | de5de2a | 2018-11-02 19:51:10 +0530 | [diff] [blame] | 138 | CONFIG_SYSRESET_TI_SCI=y |
| 139 | CONFIG_TIMER=y |
| 140 | CONFIG_SPL_TIMER=y |
| 141 | CONFIG_OMAP_TIMER=y |
Andreas Dannenberg | f595cac | 2019-06-04 17:55:51 -0500 | [diff] [blame] | 142 | CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 |