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git01.mediatek.com / filogic / uboot / 137ab1cd7378544ced956510e47107f5399aa1e8 / . / arch / arm / cpu / arm720t / start.S
blob: 9ad1f031429cc9e1ac192b381e4c05e67639123d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]2/*
3 * armboot - Startup Code for ARM720 CPU-core
4 *
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]5 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
6 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]7 */
8
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]9#include <asm-offsets.h>
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]10#include <config.h>
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]11
12/*
13 *************************************************************************
14 *
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]15 * Startup Code (reset vector)
16 *
wdenk927034e2004-02-08 19:38:38 +0000[diff] [blame]17 * do important init only if we don't start from RAM!
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]18 * relocate armboot to ram
19 * setup stack
20 * jump to second stage
21 *
22 *************************************************************************
23 */
24
Albert ARIBAUD9852cc62014-04-15 16:13:51 +0200[diff] [blame]25 .globl reset
Heiko Schochercad80e12010-09-17 13:10:52 +0200[diff] [blame]26
27reset:
28 /*
29 * set the cpu to SVC32 mode
30 */
31 mrs r0,cpsr
32 bic r0,r0,#0x1f
33 orr r0,r0,#0xd3
34 msr cpsr,r0
35
36 /*
37 * we do sys-critical inits only at reboot,
38 * not when booting from ram!
39 */
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]40#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
41 !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
Heiko Schochercad80e12010-09-17 13:10:52 +0200[diff] [blame]42 bl cpu_init_crit
43#endif
44
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]45 bl _main
Heiko Schochercad80e12010-09-17 13:10:52 +0200[diff] [blame]46
47/*------------------------------------------------------------------------------*/
48
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]49 .globl c_runtime_cpu_setup
50c_runtime_cpu_setup:
51
52 mov pc, lr
53
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]54/*
55 *************************************************************************
56 *
57 * CPU_init_critical registers
58 *
59 * setup important registers
60 * setup memory timing
61 *
62 *************************************************************************
63 */
64
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]65#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
66 !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]67cpu_init_crit:
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]68
Wolfgang Denk7f88a5e2005-10-06 17:08:18 +0200[diff] [blame]69 mov ip, lr
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]70 /*
71 * before relocating, we have to setup RAM timing
wdenk927034e2004-02-08 19:38:38 +0000[diff] [blame]72 * because memory timing is board-dependent, you will
wdenk336b2bc2005-04-02 23:52:25 +0000[diff] [blame]73 * find a lowlevel_init.S in your board directory.
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]74 */
wdenk336b2bc2005-04-02 23:52:25 +0000[diff] [blame]75 bl lowlevel_init
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]76 mov lr, ip
77
78 mov pc, lr
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]79#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */