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git01.mediatek.com / filogic / uboot / 131e0b0c49135b3d2acd79fecd2261be302ce8b5 / . / drivers / pci / Kconfig
blob: e2a1c0a4096b2e84b99f726b98fbcebbe5ddb94c [file] [log] [blame]
Tom Rinif48e0252016-10-26 17:15:37 -0400[diff] [blame]1menuconfig PCI
2 bool "PCI support"
Bin Meng00a17fd2017-07-30 06:23:09 -0700[diff] [blame]3 default y if PPC
Tom Rinif48e0252016-10-26 17:15:37 -0400[diff] [blame]4 help
5 Enable support for PCI (Peripheral Interconnect Bus), a type of bus
6 used on some devices to allow the CPU to communicate with its
7 peripherals.
8
9if PCI
Simon Glassb94dc892015-03-05 12:25:25 -0700[diff] [blame]10
11config DM_PCI
Marcel Ziswiler84c45602016-12-19 15:38:05 +0100[diff] [blame]12 bool "Enable driver model for PCI"
Simon Glassb94dc892015-03-05 12:25:25 -0700[diff] [blame]13 depends on DM
14 help
15 Use driver model for PCI. Driver model is the new method for
16 orgnising devices in U-Boot. For PCI, driver model keeps track of
17 available PCI devices, allows scanning of PCI buses and provides
18 device configuration support.
19
Simon Glasseca7b0d2015-11-26 19:51:30 -0700[diff] [blame]20config DM_PCI_COMPAT
21 bool "Enable compatible functions for PCI"
22 depends on DM_PCI
23 help
24 Enable compatibility functions for PCI so that old code can be used
25 with CONFIG_DM_PCI enabled. This should be used as an interim
26 measure when porting a board to use driver model for PCI. Once the
27 board is fully supported, this option should be disabled.
28
Bin Meng2f49e2e2016-10-16 23:35:18 -0700[diff] [blame]29config PCI_PNP
30 bool "Enable Plug & Play support for PCI"
31 depends on PCI || DM_PCI
32 default y
33 help
34 Enable PCI memory and I/O space resource allocation and assignment.
35
Shadi Ammouri3b386452016-10-27 13:29:41 +0200[diff] [blame]36config PCIE_DW_MVEBU
37 bool "Enable Armada-8K PCIe driver (DesignWare core)"
38 default n
39 depends on DM_PCI
40 depends on ARMADA_8K
41 help
42 Say Y here if you want to enable PCIe controller support on
43 Armada-8K SoCs. The PCIe controller on Armada-8K is based on
44 DesignWare hardware.
45
Simon Glass4d857552015-03-05 12:25:27 -0700[diff] [blame]46config PCI_SANDBOX
47 bool "Sandbox PCI support"
48 depends on SANDBOX && DM_PCI
49 help
50 Support PCI on sandbox, as an emulated bus. This permits testing of
51 PCI feature such as bus scanning, device configuration and device
52 access. The available (emulated) devices are defined statically in
53 the device tree but the normal PCI scan technique is used to find
54 then.
55
Simon Glassc78e3272015-11-19 20:26:55 -0700[diff] [blame]56config PCI_TEGRA
57 bool "Tegra PCI support"
58 depends on TEGRA
Stephen Warren86f6a942016-08-05 16:10:34 -0600[diff] [blame]59 depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
Simon Glassc78e3272015-11-19 20:26:55 -0700[diff] [blame]60 help
61 Enable support for the PCIe controller found on some generations of
62 Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
63 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
64 with a total of 5 lanes. Some boards require this for Ethernet
65 support to work (e.g. beaver, jetson-tk1).
66
Paul Burtonc893f212016-09-08 07:47:31 +0100[diff] [blame]67config PCI_XILINX
68 bool "Xilinx AXI Bridge for PCI Express"
69 depends on DM_PCI
70 help
71 Enable support for the Xilinx AXI bridge for PCI express, an IP block
72 which can be used on some generations of Xilinx FPGAs.
73
Minghuan Lianc1067842016-12-13 14:54:17 +0800[diff] [blame]74config PCIE_LAYERSCAPE
75 bool "Layerscape PCIe support"
76 depends on DM_PCI
77 help
78 Support Layerscape PCIe. The Layerscape SoC may have one or several
79 PCIe controllers. The PCIe may works in RC or EP mode according to
80 RCW[HOST_AGT_PEX] setting.
81
Tom Rinif48e0252016-10-26 17:15:37 -0400[diff] [blame]82endif