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git01.mediatek.com / filogic / uboot / 1240d88b4264c6aa9e7634e7340fc75673617560 / . / arch / arm / mach-uniphier / spl_board_init.c
blob: 1272b4e25c08b8d75e182695c08a584f3640dc04 [file] [log] [blame]
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]1/*
2 * Copyright (C) 2015-2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <debug_uart.h>
10#include <spl.h>
11
12#include "init.h"
13#include "micro-support-card.h"
14#include "soc-info.h"
15
16struct uniphier_spl_initdata {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]17 unsigned int soc_id;
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]18 void (*bcu_init)(const struct uniphier_board_data *bd);
19 void (*early_clk_init)(void);
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]20 int (*dpll_init)(const struct uniphier_board_data *bd);
21 int (*memconf_init)(const struct uniphier_board_data *bd);
22 void (*dram_clk_init)(void);
23 int (*umc_init)(const struct uniphier_board_data *bd);
24};
25
26static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]27#if defined(CONFIG_ARCH_UNIPHIER_LD4)
28 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]29 .soc_id = UNIPHIER_LD4_ID,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]30 .bcu_init = uniphier_ld4_bcu_init,
Masahiro Yamadad3c14612017-08-13 09:01:13 +0900[diff] [blame]31 .early_clk_init = uniphier_ld4_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]32 .dpll_init = uniphier_ld4_dpll_init,
33 .memconf_init = uniphier_memconf_2ch_init,
Masahiro Yamadad3c14612017-08-13 09:01:13 +0900[diff] [blame]34 .dram_clk_init = uniphier_ld4_dram_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]35 .umc_init = uniphier_ld4_umc_init,
36 },
37#endif
38#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
39 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]40 .soc_id = UNIPHIER_PRO4_ID,
Masahiro Yamadad3c14612017-08-13 09:01:13 +0900[diff] [blame]41 .early_clk_init = uniphier_ld4_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]42 .dpll_init = uniphier_pro4_dpll_init,
43 .memconf_init = uniphier_memconf_2ch_init,
Masahiro Yamadad3c14612017-08-13 09:01:13 +0900[diff] [blame]44 .dram_clk_init = uniphier_ld4_dram_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]45 .umc_init = uniphier_pro4_umc_init,
46 },
47#endif
48#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
49 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]50 .soc_id = UNIPHIER_SLD8_ID,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]51 .bcu_init = uniphier_ld4_bcu_init,
Masahiro Yamadad3c14612017-08-13 09:01:13 +0900[diff] [blame]52 .early_clk_init = uniphier_ld4_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]53 .dpll_init = uniphier_sld8_dpll_init,
54 .memconf_init = uniphier_memconf_2ch_init,
Masahiro Yamadad3c14612017-08-13 09:01:13 +0900[diff] [blame]55 .dram_clk_init = uniphier_ld4_dram_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]56 .umc_init = uniphier_sld8_umc_init,
57 },
58#endif
59#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
60 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]61 .soc_id = UNIPHIER_PRO5_ID,
Masahiro Yamadad3c14612017-08-13 09:01:13 +0900[diff] [blame]62 .early_clk_init = uniphier_ld4_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]63 .dpll_init = uniphier_pro5_dpll_init,
64 .memconf_init = uniphier_memconf_2ch_init,
65 .dram_clk_init = uniphier_pro5_dram_clk_init,
66 .umc_init = uniphier_pro5_umc_init,
67 },
68#endif
69#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
70 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]71 .soc_id = UNIPHIER_PXS2_ID,
Masahiro Yamadad3c14612017-08-13 09:01:13 +0900[diff] [blame]72 .early_clk_init = uniphier_ld4_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]73 .dpll_init = uniphier_pxs2_dpll_init,
74 .memconf_init = uniphier_memconf_3ch_init,
75 .dram_clk_init = uniphier_pxs2_dram_clk_init,
76 .umc_init = uniphier_pxs2_umc_init,
77 },
78#endif
79#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
80 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]81 .soc_id = UNIPHIER_LD6B_ID,
Masahiro Yamadad3c14612017-08-13 09:01:13 +0900[diff] [blame]82 .early_clk_init = uniphier_ld4_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]83 .dpll_init = uniphier_pxs2_dpll_init,
84 .memconf_init = uniphier_memconf_3ch_init,
85 .dram_clk_init = uniphier_pxs2_dram_clk_init,
86 .umc_init = uniphier_pxs2_umc_init,
87 },
88#endif
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]89};
Masahiro Yamada1b818982017-01-21 18:05:27 +0900[diff] [blame]90UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata, uniphier_spl_initdata)
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]91
92void spl_board_init(void)
93{
94 const struct uniphier_board_data *bd;
95 const struct uniphier_spl_initdata *initdata;
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]96 int ret;
97
98#ifdef CONFIG_DEBUG_UART
99 debug_uart_init();
100#endif
101
102 bd = uniphier_get_board_param();
103 if (!bd)
104 hang();
105
Masahiro Yamada1b818982017-01-21 18:05:27 +0900[diff] [blame]106 initdata = uniphier_get_spl_initdata();
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]107 if (!initdata)
108 hang();
109
110 if (initdata->bcu_init)
111 initdata->bcu_init(bd);
112
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]113 initdata->early_clk_init();
114
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]115#ifdef CONFIG_SPL_SERIAL_SUPPORT
116 preloader_console_init();
117#endif
118
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]119 ret = initdata->dpll_init(bd);
120 if (ret) {
121 pr_err("failed to init DPLL\n");
122 hang();
123 }
124
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]125 ret = initdata->memconf_init(bd);
126 if (ret) {
127 pr_err("failed to init MEMCONF\n");
128 hang();
129 }
130
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]131 initdata->dram_clk_init();
132
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]133 ret = initdata->umc_init(bd);
134 if (ret) {
135 pr_err("failed to init DRAM\n");
136 hang();
137 }
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]138}