York Sun | 9b85a48 | 2013-06-27 10:48:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 3 | * |
York Sun | b33ba9a | 2013-08-12 14:57:12 -0700 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
York Sun | 9b85a48 | 2013-06-27 10:48:29 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __DDR_H__ |
| 8 | #define __DDR_H__ |
| 9 | struct board_specific_parameters { |
| 10 | u32 n_ranks; |
| 11 | u32 datarate_mhz_high; |
| 12 | u32 rank_gb; |
| 13 | u32 clk_adjust; |
| 14 | u32 wrlvl_start; |
| 15 | u32 wrlvl_ctl_2; |
| 16 | u32 wrlvl_ctl_3; |
| 17 | u32 cpo; |
| 18 | u32 write_data_delay; |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 19 | u32 force_2t; |
York Sun | 9b85a48 | 2013-06-27 10:48:29 -0700 | [diff] [blame] | 20 | }; |
| 21 | |
| 22 | /* |
| 23 | * These tables contain all valid speeds we want to override with board |
| 24 | * specific parameters. datarate_mhz_high values need to be in ascending order |
| 25 | * for each n_ranks group. |
| 26 | */ |
| 27 | |
York Sun | 9b85a48 | 2013-06-27 10:48:29 -0700 | [diff] [blame] | 28 | static const struct board_specific_parameters udimm0[] = { |
| 29 | /* |
| 30 | * memory controller 0 |
| 31 | * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
| 32 | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
| 33 | */ |
Shengzhou Liu | f1510e6 | 2016-05-04 10:20:22 +0800 | [diff] [blame] | 34 | {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
| 35 | {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, |
| 36 | {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, |
| 37 | {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, |
| 38 | {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, |
| 39 | {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, |
| 40 | {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
| 41 | {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
| 42 | {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, |
| 43 | {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, |
York Sun | 9b85a48 | 2013-06-27 10:48:29 -0700 | [diff] [blame] | 44 | {} |
| 45 | }; |
| 46 | |
| 47 | static const struct board_specific_parameters rdimm0[] = { |
| 48 | /* |
| 49 | * memory controller 0 |
| 50 | * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
| 51 | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
| 52 | */ |
Shengzhou Liu | f1510e6 | 2016-05-04 10:20:22 +0800 | [diff] [blame] | 53 | {4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, |
| 54 | {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, |
| 55 | {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, |
| 56 | {2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, |
| 57 | {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, |
| 58 | {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, |
| 59 | {1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, |
| 60 | {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, |
| 61 | {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, |
York Sun | 9b85a48 | 2013-06-27 10:48:29 -0700 | [diff] [blame] | 62 | {} |
| 63 | }; |
| 64 | |
York Sun | 9b85a48 | 2013-06-27 10:48:29 -0700 | [diff] [blame] | 65 | /* |
| 66 | * The three slots have slightly different timing. The center values are good |
| 67 | * for all slots. We use identical speed tables for them. In future use, if |
| 68 | * DIMMs require separated tables, make more entries as needed. |
| 69 | */ |
| 70 | static const struct board_specific_parameters *udimms[] = { |
| 71 | udimm0, |
| 72 | }; |
| 73 | |
| 74 | /* |
| 75 | * The three slots have slightly different timing. See comments above. |
| 76 | */ |
| 77 | static const struct board_specific_parameters *rdimms[] = { |
| 78 | rdimm0, |
| 79 | }; |
| 80 | |
| 81 | |
| 82 | #endif |