| Kever Yang | 38a99b6 | 2019-11-15 11:04:34 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Rockchip Electronics Co., Ltd |
| 4 | */ |
| 5 | |
| 6 | #ifndef _ASM_ARCH_SDRAM_COMMON_H |
| 7 | #define _ASM_ARCH_SDRAM_COMMON_H |
| 8 | |
| 9 | struct sdram_cap_info { |
| 10 | unsigned int rank; |
| 11 | /* dram column number, 0 means this channel is invalid */ |
| 12 | unsigned int col; |
| 13 | /* dram bank number, 3:8bank, 2:4bank */ |
| 14 | unsigned int bk; |
| 15 | /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ |
| 16 | unsigned int bw; |
| 17 | /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ |
| 18 | unsigned int dbw; |
| 19 | /* |
| 20 | * row_3_4 = 1: 6Gb or 12Gb die |
| 21 | * row_3_4 = 0: normal die, power of 2 |
| 22 | */ |
| 23 | unsigned int row_3_4; |
| 24 | unsigned int cs0_row; |
| 25 | unsigned int cs1_row; |
| 26 | unsigned int cs0_high16bit_row; |
| 27 | unsigned int cs1_high16bit_row; |
| 28 | unsigned int ddrconfig; |
| 29 | }; |
| 30 | |
| 31 | struct sdram_base_params { |
| 32 | unsigned int ddr_freq; |
| 33 | unsigned int dramtype; |
| 34 | unsigned int num_channels; |
| 35 | unsigned int stride; |
| 36 | unsigned int odt; |
| 37 | }; |
| 38 | |
| 39 | #if !defined(CONFIG_RAM_ROCKCHIP_DEBUG) |
| 40 | inline void sdram_print_dram_type(unsigned char dramtype) |
| 41 | { |
| 42 | } |
| 43 | |
| 44 | inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info, |
| 45 | struct sdram_base_params *base) |
| 46 | { |
| 47 | } |
| 48 | |
| 49 | inline void sdram_print_stride(unsigned int stride) |
| 50 | { |
| 51 | } |
| 52 | #else |
| 53 | void sdram_print_dram_type(unsigned char dramtype); |
| 54 | void sdram_print_ddr_info(struct sdram_cap_info *cap_info, |
| 55 | struct sdram_base_params *base); |
| 56 | void sdram_print_stride(unsigned int stride); |
| 57 | #endif /* CONFIG_RAM_ROCKCHIP_DEBUG */ |
| 58 | |
| 59 | #endif |