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git01.mediatek.com / filogic / uboot / 11206f4d4d2923d395bfe404ed38d0f988ad390d / . / include / dm / uclass-id.h
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Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]1/*
2 * Copyright (c) 2013 Google, Inc
3 *
4 * (C) Copyright 2012
5 * Pavel Herrmann <morpheus.ibis@gmail.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef _DM_UCLASS_ID_H
11#define _DM_UCLASS_ID_H
12
13/* TODO(sjg@chromium.org): this could be compile-time generated */
14enum uclass_id {
15 /* These are used internally by driver model */
16 UCLASS_ROOT = 0,
17 UCLASS_DEMO,
18 UCLASS_TEST,
19 UCLASS_TEST_FDT,
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]20 UCLASS_TEST_BUS,
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]21 UCLASS_TEST_PROBE,
Simon Glass10a4a332014-10-13 23:41:53 -0600[diff] [blame]22 UCLASS_SPI_EMUL, /* sandbox SPI device emulator */
Simon Glassdaa54702014-12-10 08:55:49 -0700[diff] [blame]23 UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
Simon Glassd9e90bb2015-03-05 12:25:28 -0700[diff] [blame]24 UCLASS_PCI_EMUL, /* sandbox PCI device emulator */
Simon Glass59d66d22015-03-25 12:22:37 -0600[diff] [blame]25 UCLASS_USB_EMUL, /* sandbox USB bus device emulator */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]26 UCLASS_SIMPLE_BUS, /* bus with child devices */
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]27
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]28 /* U-Boot uclasses start here - in alphabetical order */
Przemyslaw Marczake0cb85b2015-10-27 13:08:00 +0100[diff] [blame]29 UCLASS_ADC, /* Analog-to-digital converter */
Simon Glass85ee1652016-05-01 11:35:52 -0600[diff] [blame]30 UCLASS_AHCI, /* SATA disk controller */
Simon Glasscceee552016-02-29 15:25:55 -0700[diff] [blame]31 UCLASS_BLK, /* Block device */
Simon Glass36ad2342015-06-23 15:39:15 -0600[diff] [blame]32 UCLASS_CLK, /* Clock source, e.g. used by peripherals */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]33 UCLASS_CPU, /* CPU, typically part of an SoC */
34 UCLASS_CROS_EC, /* Chrome OS EC */
Simon Glass7d3d7762016-01-21 19:45:00 -0700[diff] [blame]35 UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
Mugunthan V N8c3c9182016-02-15 15:31:37 +0530[diff] [blame]36 UCLASS_DMA, /* Direct Memory Access */
Heinrich Schuchardt11206f42018-01-21 19:29:30 +0100[diff] [blame^]37 UCLASS_EFI, /* EFI managed devices */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]38 UCLASS_ETH, /* Ethernet device */
Simon Glasscebcebb2014-07-23 06:55:17 -0600[diff] [blame]39 UCLASS_GPIO, /* Bank of general-purpose I/O pins */
Masahiro Yamada836c55d2017-04-14 11:10:24 +0900[diff] [blame]40 UCLASS_FIRMWARE, /* Firmware */
Simon Glassc7a58902014-12-10 08:55:47 -0700[diff] [blame]41 UCLASS_I2C, /* I2C bus */
Simon Glass6ca4ba02014-12-10 08:55:54 -0700[diff] [blame]42 UCLASS_I2C_EEPROM, /* I2C EEPROM device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]43 UCLASS_I2C_GENERIC, /* Generic I2C device */
Simon Glass2a80c402015-08-03 08:19:21 -0600[diff] [blame]44 UCLASS_I2C_MUX, /* I2C multiplexer */
Bin Mengb650afa2017-09-10 05:12:51 -0700[diff] [blame]45 UCLASS_IDE, /* IDE device */
Simon Glass18a8e092016-01-19 21:32:25 -0700[diff] [blame]46 UCLASS_IRQ, /* Interrupt controller */
Simon Glass02f0c282015-09-08 11:15:11 -0600[diff] [blame]47 UCLASS_KEYBOARD, /* Keyboard input device */
Simon Glasscce3aed2015-06-23 15:38:45 -0600[diff] [blame]48 UCLASS_LED, /* Light-emitting diode (LED) */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]49 UCLASS_LPC, /* x86 'low pin count' interface */
Stephen Warrend0107832016-05-13 15:50:29 -0600[diff] [blame]50 UCLASS_MAILBOX, /* Mailbox controller */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]51 UCLASS_MASS_STORAGE, /* Mass storage device */
Thomas Choub1ed6862015-10-07 20:20:51 +0800[diff] [blame]52 UCLASS_MISC, /* Miscellaneous device */
Simon Glass1e8eb1b2015-06-23 15:38:48 -0600[diff] [blame]53 UCLASS_MMC, /* SD / MMC card or chip */
Ruchika Gupta98ebb122015-01-23 16:01:52 +0530[diff] [blame]54 UCLASS_MOD_EXP, /* RSA Mod Exp device */
Thomas Choue51b65e2015-11-07 14:20:31 +0800[diff] [blame]55 UCLASS_MTD, /* Memory Technology Device (MTD) device */
Simon Glass29ce97e2016-01-17 16:11:14 -0700[diff] [blame]56 UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */
Zhikang Zhang182fccd2017-08-03 02:30:56 -0700[diff] [blame]57 UCLASS_NVME, /* NVM Express device */
Simon Glass14d1c8e2016-01-21 19:44:58 -0700[diff] [blame]58 UCLASS_PANEL, /* Display panel, such as an LCD */
Simon Glass8f790482016-01-21 19:44:56 -0700[diff] [blame]59 UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]60 UCLASS_PCH, /* x86 platform controller hub */
Simon Glassb94dc892015-03-05 12:25:25 -0700[diff] [blame]61 UCLASS_PCI, /* PCI bus */
62 UCLASS_PCI_GENERIC, /* Generic PCI bus device */
Jean-Jacques Hiblot48447782017-04-24 11:51:27 +0200[diff] [blame]63 UCLASS_PHY, /* Physical Layer (PHY) device */
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900[diff] [blame]64 UCLASS_PINCONFIG, /* Pin configuration node device */
Bin Meng1cc7ecd2016-06-22 02:29:47 -0700[diff] [blame]65 UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
Simon Glass682ae862015-05-22 15:42:14 -0600[diff] [blame]66 UCLASS_PMIC, /* PMIC I/O device */
Simon Glassb3f07562016-01-21 19:44:54 -0700[diff] [blame]67 UCLASS_PWM, /* Pulse-width modulator */
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]68 UCLASS_POWER_DOMAIN, /* (SoC) Power domains */
Simon Glassc9795172016-01-21 19:43:31 -0700[diff] [blame]69 UCLASS_PWRSEQ, /* Power sequence device */
Bin Meng1cc7ecd2016-06-22 02:29:47 -0700[diff] [blame]70 UCLASS_RAM, /* RAM controller */
Simon Glass682ae862015-05-22 15:42:14 -0600[diff] [blame]71 UCLASS_REGULATOR, /* Regulator device */
Nishanth Menon08b9dc22015-09-17 15:42:39 -0500[diff] [blame]72 UCLASS_REMOTEPROC, /* Remote Processor device */
Stephen Warren185ad872016-06-17 09:43:58 -0600[diff] [blame]73 UCLASS_RESET, /* Reset controller device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]74 UCLASS_RTC, /* Real time clock device */
Michal Simekc886f352016-09-08 15:06:45 +0200[diff] [blame]75 UCLASS_SCSI, /* SCSI device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]76 UCLASS_SERIAL, /* Serial UART */
77 UCLASS_SPI, /* SPI bus */
Mateusz Kulikowski946797f2016-03-31 23:12:27 +0200[diff] [blame]78 UCLASS_SPMI, /* System Power Management Interface bus */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]79 UCLASS_SPI_FLASH, /* SPI flash */
Simon Glass682ae862015-05-22 15:42:14 -0600[diff] [blame]80 UCLASS_SPI_GENERIC, /* Generic SPI flash target */
Simon Glass6a84aaf2015-06-23 15:38:43 -0600[diff] [blame]81 UCLASS_SYSCON, /* System configuration device */
Stephen Warren859f2562016-05-12 12:03:35 -0600[diff] [blame]82 UCLASS_SYSRESET, /* System reset device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]83 UCLASS_THERMAL, /* Thermal sensor */
Thomas Choufb798b12015-10-09 13:46:34 +0800[diff] [blame]84 UCLASS_TIMER, /* Timer device */
Simon Glass6c7a2322015-08-22 18:31:31 -0600[diff] [blame]85 UCLASS_TPM, /* Trusted Platform Module TIS interface */
Simon Glass9b82eeb2015-03-25 12:21:59 -0600[diff] [blame]86 UCLASS_USB, /* USB bus */
Simon Glassc79173e2015-03-25 12:22:31 -0600[diff] [blame]87 UCLASS_USB_DEV_GENERIC, /* USB generic device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]88 UCLASS_USB_HUB, /* USB hub */
Simon Glass623d28f2016-01-18 19:52:15 -0700[diff] [blame]89 UCLASS_VIDEO, /* Video or LCD device */
Simon Glass7cf17572015-07-02 18:16:08 -0600[diff] [blame]90 UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */
Simon Glass84c7fb32016-01-18 19:52:17 -0700[diff] [blame]91 UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]92 UCLASS_WDT, /* Watchdot Timer driver */
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]93
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]94 UCLASS_COUNT,
95 UCLASS_INVALID = -1,
96};
97
98#endif