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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00002/*
Heiko Schocher479a4cf2013-01-29 08:53:15 +01003 * (C) Copyright 2009
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * Changes for multibus/multiadapter I2C support.
6 *
wdenkc6097192002-11-03 00:24:07 +00007 * (C) Copyright 2001, 2002
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
wdenkc6097192002-11-03 00:24:07 +000010 * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
11 * vanbaren@cideas.com. It was heavily influenced by LiMon, written by
12 * Neil Russell.
Simon Glasscb052ff2016-11-23 06:34:44 -070013 *
14 * NOTE: This driver should be converted to driver model before June 2017.
15 * Please see doc/driver-model/i2c-howto.txt for instructions.
wdenkc6097192002-11-03 00:24:07 +000016 */
17
18#include <common.h>
Ryan Mallon78d66912011-01-27 08:54:15 +130019#if defined(CONFIG_AT91FAMILY)
wdenk20dd2fa2004-11-21 00:06:33 +000020#include <asm/io.h>
21#include <asm/arch/hardware.h>
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010022#include <asm/arch/at91_pio.h>
Andreas Bießmanna8649792013-10-30 15:18:18 +010023#ifdef CONFIG_ATMEL_LEGACY
Daniel Gorsulowski5a2d8842009-05-18 13:20:54 +020024#include <asm/arch/gpio.h>
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010025#endif
Daniel Gorsulowski5a2d8842009-05-18 13:20:54 +020026#endif
wdenkc6097192002-11-03 00:24:07 +000027#include <i2c.h>
28
Mike Frysingeree12d542010-07-21 13:38:02 -040029#if defined(CONFIG_SOFT_I2C_GPIO_SCL)
30# include <asm/gpio.h>
31
32# ifndef I2C_GPIO_SYNC
33# define I2C_GPIO_SYNC
34# endif
35
36# ifndef I2C_INIT
37# define I2C_INIT \
38 do { \
39 gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \
40 gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \
41 } while (0)
42# endif
43
44# ifndef I2C_ACTIVE
45# define I2C_ACTIVE do { } while (0)
46# endif
47
48# ifndef I2C_TRISTATE
49# define I2C_TRISTATE do { } while (0)
50# endif
51
52# ifndef I2C_READ
53# define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA)
54# endif
55
56# ifndef I2C_SDA
57# define I2C_SDA(bit) \
58 do { \
59 if (bit) \
60 gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \
61 else \
62 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \
63 I2C_GPIO_SYNC; \
64 } while (0)
65# endif
66
67# ifndef I2C_SCL
68# define I2C_SCL(bit) \
69 do { \
70 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \
71 I2C_GPIO_SYNC; \
72 } while (0)
73# endif
74
75# ifndef I2C_DELAY
76# define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
77# endif
78
79#endif
80
wdenkc6097192002-11-03 00:24:07 +000081/* #define DEBUG_I2C */
82
Wolfgang Denk6405a152006-03-31 18:32:53 +020083DECLARE_GLOBAL_DATA_PTR;
Heiko Schocher479a4cf2013-01-29 08:53:15 +010084
85#ifndef I2C_SOFT_DECLARATIONS
Heiko Schocher479a4cf2013-01-29 08:53:15 +010086# define I2C_SOFT_DECLARATIONS
Wolfgang Denk6405a152006-03-31 18:32:53 +020087#endif
88
Marek Vasuta3c41ba2013-08-01 12:32:20 +020089#if !defined(CONFIG_SYS_I2C_SOFT_SPEED)
90#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
Heiko Schocher479a4cf2013-01-29 08:53:15 +010091#endif
Marek Vasuta3c41ba2013-08-01 12:32:20 +020092#if !defined(CONFIG_SYS_I2C_SOFT_SLAVE)
93#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
Heiko Schocher479a4cf2013-01-29 08:53:15 +010094#endif
95
wdenkc6097192002-11-03 00:24:07 +000096/*-----------------------------------------------------------------------
97 * Definitions
98 */
wdenkc6097192002-11-03 00:24:07 +000099#define RETRIES 0
100
wdenkc6097192002-11-03 00:24:07 +0000101#define I2C_ACK 0 /* PD_SDA level to ack a byte */
102#define I2C_NOACK 1 /* PD_SDA level to noack a byte */
103
104
105#ifdef DEBUG_I2C
106#define PRINTD(fmt,args...) do { \
wdenkc6097192002-11-03 00:24:07 +0000107 printf (fmt ,##args); \
108 } while (0)
109#else
110#define PRINTD(fmt,args...)
111#endif
112
113/*-----------------------------------------------------------------------
114 * Local functions
115 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
wdenkc6097192002-11-03 00:24:07 +0000117static void send_reset (void);
Heiko Schocher0e2f2c52008-10-15 09:38:38 +0200118#endif
wdenkc6097192002-11-03 00:24:07 +0000119static void send_start (void);
120static void send_stop (void);
121static void send_ack (int);
122static int write_byte (uchar byte);
123static uchar read_byte (int);
124
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
wdenkc6097192002-11-03 00:24:07 +0000126/*-----------------------------------------------------------------------
127 * Send a reset sequence consisting of 9 clocks with the data signal high
128 * to clock any confused device back into an idle state. Also send a
129 * <stop> at the end of the sequence for belts & suspenders.
130 */
131static void send_reset(void)
132{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200133 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000134 int j;
135
wdenka6db71d2003-04-08 23:25:21 +0000136 I2C_SCL(1);
wdenkc6097192002-11-03 00:24:07 +0000137 I2C_SDA(1);
wdenka6db71d2003-04-08 23:25:21 +0000138#ifdef I2C_INIT
139 I2C_INIT;
140#endif
141 I2C_TRISTATE;
wdenkc6097192002-11-03 00:24:07 +0000142 for(j = 0; j < 9; j++) {
143 I2C_SCL(0);
144 I2C_DELAY;
145 I2C_DELAY;
146 I2C_SCL(1);
147 I2C_DELAY;
148 I2C_DELAY;
149 }
150 send_stop();
151 I2C_TRISTATE;
152}
Heiko Schocher0e2f2c52008-10-15 09:38:38 +0200153#endif
wdenkc6097192002-11-03 00:24:07 +0000154
155/*-----------------------------------------------------------------------
156 * START: High -> Low on SDA while SCL is High
157 */
158static void send_start(void)
159{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200160 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000161
162 I2C_DELAY;
163 I2C_SDA(1);
164 I2C_ACTIVE;
165 I2C_DELAY;
166 I2C_SCL(1);
167 I2C_DELAY;
168 I2C_SDA(0);
169 I2C_DELAY;
170}
171
172/*-----------------------------------------------------------------------
173 * STOP: Low -> High on SDA while SCL is High
174 */
175static void send_stop(void)
176{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200177 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000178
179 I2C_SCL(0);
180 I2C_DELAY;
181 I2C_SDA(0);
182 I2C_ACTIVE;
183 I2C_DELAY;
184 I2C_SCL(1);
185 I2C_DELAY;
186 I2C_SDA(1);
187 I2C_DELAY;
188 I2C_TRISTATE;
189}
190
wdenkc6097192002-11-03 00:24:07 +0000191/*-----------------------------------------------------------------------
192 * ack should be I2C_ACK or I2C_NOACK
193 */
194static void send_ack(int ack)
195{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200196 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000197
wdenkc6097192002-11-03 00:24:07 +0000198 I2C_SCL(0);
199 I2C_DELAY;
wdenkc6097192002-11-03 00:24:07 +0000200 I2C_ACTIVE;
Wolfgang Denkd4a61102006-03-13 00:50:48 +0100201 I2C_SDA(ack);
wdenkc6097192002-11-03 00:24:07 +0000202 I2C_DELAY;
203 I2C_SCL(1);
204 I2C_DELAY;
205 I2C_DELAY;
206 I2C_SCL(0);
207 I2C_DELAY;
208}
209
wdenkc6097192002-11-03 00:24:07 +0000210/*-----------------------------------------------------------------------
211 * Send 8 bits and look for an acknowledgement.
212 */
213static int write_byte(uchar data)
214{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200215 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000216 int j;
217 int nack;
218
219 I2C_ACTIVE;
220 for(j = 0; j < 8; j++) {
221 I2C_SCL(0);
222 I2C_DELAY;
223 I2C_SDA(data & 0x80);
224 I2C_DELAY;
225 I2C_SCL(1);
226 I2C_DELAY;
227 I2C_DELAY;
228
229 data <<= 1;
230 }
231
232 /*
233 * Look for an <ACK>(negative logic) and return it.
234 */
235 I2C_SCL(0);
236 I2C_DELAY;
237 I2C_SDA(1);
238 I2C_TRISTATE;
239 I2C_DELAY;
240 I2C_SCL(1);
241 I2C_DELAY;
242 I2C_DELAY;
243 nack = I2C_READ;
244 I2C_SCL(0);
245 I2C_DELAY;
246 I2C_ACTIVE;
247
248 return(nack); /* not a nack is an ack */
249}
250
wdenkc6097192002-11-03 00:24:07 +0000251/*-----------------------------------------------------------------------
252 * if ack == I2C_ACK, ACK the byte so can continue reading, else
253 * send I2C_NOACK to end the read.
254 */
255static uchar read_byte(int ack)
256{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200257 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000258 int data;
259 int j;
260
261 /*
262 * Read 8 bits, MSB first.
263 */
264 I2C_TRISTATE;
Haavard Skinnemoen15fb0a12008-05-16 11:08:11 +0200265 I2C_SDA(1);
wdenkc6097192002-11-03 00:24:07 +0000266 data = 0;
267 for(j = 0; j < 8; j++) {
268 I2C_SCL(0);
269 I2C_DELAY;
270 I2C_SCL(1);
271 I2C_DELAY;
272 data <<= 1;
273 data |= I2C_READ;
274 I2C_DELAY;
275 }
276 send_ack(ack);
277
278 return(data);
279}
280
wdenkc6097192002-11-03 00:24:07 +0000281/*-----------------------------------------------------------------------
282 * Initialization
283 */
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100284static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
wdenkc6097192002-11-03 00:24:07 +0000285{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200286#if defined(CONFIG_SYS_I2C_INIT_BOARD)
Heiko Schocher0e2f2c52008-10-15 09:38:38 +0200287 /* call board specific i2c bus reset routine before accessing the */
288 /* environment, which might be in a chip on that bus. For details */
289 /* about this problem see doc/I2C_Edge_Conditions. */
290 i2c_init_board();
291#else
wdenkc6097192002-11-03 00:24:07 +0000292 /*
wdenk57b2d802003-06-27 21:31:46 +0000293 * WARNING: Do NOT save speed in a static variable: if the
294 * I2C routines are called before RAM is initialized (to read
295 * the DIMM SPD, for instance), RAM won't be usable and your
296 * system will crash.
wdenkc6097192002-11-03 00:24:07 +0000297 */
298 send_reset ();
Heiko Schocher0e2f2c52008-10-15 09:38:38 +0200299#endif
wdenkc6097192002-11-03 00:24:07 +0000300}
301
302/*-----------------------------------------------------------------------
303 * Probe to see if a chip is present. Also good for checking for the
304 * completion of EEPROM writes since the chip stops responding until
305 * the write completes (typically 10mSec).
306 */
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100307static int soft_i2c_probe(struct i2c_adapter *adap, uint8_t addr)
wdenkc6097192002-11-03 00:24:07 +0000308{
309 int rc;
310
Wolfgang Denk0a8599f2006-03-12 01:30:45 +0100311 /*
Wolfgang Denk2bad8682006-03-12 02:55:22 +0100312 * perform 1 byte write transaction with just address byte
Wolfgang Denk0a8599f2006-03-12 01:30:45 +0100313 * (fake write)
314 */
wdenkc6097192002-11-03 00:24:07 +0000315 send_start();
wdenk34b613e2002-12-17 01:51:00 +0000316 rc = write_byte ((addr << 1) | 0);
wdenkc6097192002-11-03 00:24:07 +0000317 send_stop();
318
319 return (rc ? 1 : 0);
320}
321
322/*-----------------------------------------------------------------------
323 * Read bytes
324 */
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100325static int soft_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
326 int alen, uchar *buffer, int len)
wdenkc6097192002-11-03 00:24:07 +0000327{
328 int shift;
329 PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
330 chip, addr, alen, buffer, len);
331
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200332#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
wdenkc6097192002-11-03 00:24:07 +0000333 /*
334 * EEPROM chips that implement "address overflow" are ones
335 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
336 * address and the extra bits end up in the "chip address"
337 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
338 * four 256 byte chips.
339 *
340 * Note that we consider the length of the address field to
341 * still be one byte because the extra address bits are
342 * hidden in the chip address.
343 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200344 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
wdenkc6097192002-11-03 00:24:07 +0000345
346 PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
347 chip, addr);
348#endif
349
350 /*
351 * Do the addressing portion of a write cycle to set the
352 * chip's address pointer. If the address length is zero,
353 * don't do the normal write cycle to set the address pointer,
354 * there is no address pointer in this chip.
355 */
356 send_start();
357 if(alen > 0) {
358 if(write_byte(chip << 1)) { /* write cycle */
359 send_stop();
360 PRINTD("i2c_read, no chip responded %02X\n", chip);
361 return(1);
362 }
363 shift = (alen-1) * 8;
364 while(alen-- > 0) {
365 if(write_byte(addr >> shift)) {
366 PRINTD("i2c_read, address not <ACK>ed\n");
367 return(1);
368 }
369 shift -= 8;
370 }
Andrew Dyer58c41f92008-12-29 17:36:01 -0600371
372 /* Some I2C chips need a stop/start sequence here,
373 * other chips don't work with a full stop and need
374 * only a start. Default behaviour is to send the
375 * stop/start sequence.
376 */
377#ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
378 send_start();
379#else
380 send_stop();
wdenkc6097192002-11-03 00:24:07 +0000381 send_start();
Andrew Dyer58c41f92008-12-29 17:36:01 -0600382#endif
wdenkc6097192002-11-03 00:24:07 +0000383 }
384 /*
385 * Send the chip address again, this time for a read cycle.
386 * Then read the data. On the last byte, we do a NACK instead
387 * of an ACK(len == 0) to terminate the read.
388 */
389 write_byte((chip << 1) | 1); /* read cycle */
390 while(len-- > 0) {
391 *buffer++ = read_byte(len == 0);
392 }
393 send_stop();
394 return(0);
395}
396
397/*-----------------------------------------------------------------------
398 * Write bytes
399 */
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100400static int soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
401 int alen, uchar *buffer, int len)
wdenkc6097192002-11-03 00:24:07 +0000402{
403 int shift, failures = 0;
404
405 PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
406 chip, addr, alen, buffer, len);
407
408 send_start();
409 if(write_byte(chip << 1)) { /* write cycle */
410 send_stop();
411 PRINTD("i2c_write, no chip responded %02X\n", chip);
412 return(1);
413 }
414 shift = (alen-1) * 8;
415 while(alen-- > 0) {
416 if(write_byte(addr >> shift)) {
417 PRINTD("i2c_write, address not <ACK>ed\n");
418 return(1);
419 }
420 shift -= 8;
421 }
422
423 while(len-- > 0) {
424 if(write_byte(*buffer++)) {
425 failures++;
426 }
427 }
428 send_stop();
429 return(failures);
430}
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100431
432/*
433 * Register soft i2c adapters
434 */
Dirk Eibache2493dd2015-10-28 11:46:39 +0100435U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe,
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100436 soft_i2c_read, soft_i2c_write, NULL,
437 CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
438 0)
439#if defined(I2C_SOFT_DECLARATIONS2)
Dirk Eibache2493dd2015-10-28 11:46:39 +0100440U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe,
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100441 soft_i2c_read, soft_i2c_write, NULL,
442 CONFIG_SYS_I2C_SOFT_SPEED_2,
443 CONFIG_SYS_I2C_SOFT_SLAVE_2,
444 1)
445#endif
446#if defined(I2C_SOFT_DECLARATIONS3)
Dirk Eibache2493dd2015-10-28 11:46:39 +0100447U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe,
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100448 soft_i2c_read, soft_i2c_write, NULL,
449 CONFIG_SYS_I2C_SOFT_SPEED_3,
450 CONFIG_SYS_I2C_SOFT_SLAVE_3,
451 2)
452#endif
453#if defined(I2C_SOFT_DECLARATIONS4)
Dirk Eibache2493dd2015-10-28 11:46:39 +0100454U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe,
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100455 soft_i2c_read, soft_i2c_write, NULL,
456 CONFIG_SYS_I2C_SOFT_SPEED_4,
457 CONFIG_SYS_I2C_SOFT_SLAVE_4,
458 3)
459#endif
Dirk Eibach981bacd2015-10-28 11:46:35 +0100460#if defined(I2C_SOFT_DECLARATIONS5)
Dirk Eibache2493dd2015-10-28 11:46:39 +0100461U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe,
Dirk Eibach981bacd2015-10-28 11:46:35 +0100462 soft_i2c_read, soft_i2c_write, NULL,
463 CONFIG_SYS_I2C_SOFT_SPEED_5,
464 CONFIG_SYS_I2C_SOFT_SLAVE_5,
465 4)
466#endif
467#if defined(I2C_SOFT_DECLARATIONS6)
Dirk Eibache2493dd2015-10-28 11:46:39 +0100468U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe,
Dirk Eibach981bacd2015-10-28 11:46:35 +0100469 soft_i2c_read, soft_i2c_write, NULL,
470 CONFIG_SYS_I2C_SOFT_SPEED_6,
471 CONFIG_SYS_I2C_SOFT_SLAVE_6,
472 5)
473#endif
474#if defined(I2C_SOFT_DECLARATIONS7)
Dirk Eibache2493dd2015-10-28 11:46:39 +0100475U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe,
Dirk Eibach981bacd2015-10-28 11:46:35 +0100476 soft_i2c_read, soft_i2c_write, NULL,
477 CONFIG_SYS_I2C_SOFT_SPEED_7,
478 CONFIG_SYS_I2C_SOFT_SLAVE_7,
479 6)
480#endif
481#if defined(I2C_SOFT_DECLARATIONS8)
Dirk Eibache2493dd2015-10-28 11:46:39 +0100482U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe,
Dirk Eibach981bacd2015-10-28 11:46:35 +0100483 soft_i2c_read, soft_i2c_write, NULL,
484 CONFIG_SYS_I2C_SOFT_SPEED_8,
485 CONFIG_SYS_I2C_SOFT_SLAVE_8,
486 7)
487#endif
Dirk Eibach94594332015-10-28 11:46:36 +0100488#if defined(I2C_SOFT_DECLARATIONS9)
Dirk Eibache2493dd2015-10-28 11:46:39 +0100489U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe,
Dirk Eibach94594332015-10-28 11:46:36 +0100490 soft_i2c_read, soft_i2c_write, NULL,
491 CONFIG_SYS_I2C_SOFT_SPEED_9,
492 CONFIG_SYS_I2C_SOFT_SLAVE_9,
493 8)
494#endif
495#if defined(I2C_SOFT_DECLARATIONS10)
Dirk Eibache2493dd2015-10-28 11:46:39 +0100496U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe,
Dirk Eibach94594332015-10-28 11:46:36 +0100497 soft_i2c_read, soft_i2c_write, NULL,
498 CONFIG_SYS_I2C_SOFT_SPEED_10,
499 CONFIG_SYS_I2C_SOFT_SLAVE_10,
500 9)
501#endif
502#if defined(I2C_SOFT_DECLARATIONS11)
503U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe,
504 soft_i2c_read, soft_i2c_write, NULL,
505 CONFIG_SYS_I2C_SOFT_SPEED_11,
506 CONFIG_SYS_I2C_SOFT_SLAVE_11,
507 10)
508#endif
509#if defined(I2C_SOFT_DECLARATIONS12)
510U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe,
511 soft_i2c_read, soft_i2c_write, NULL,
512 CONFIG_SYS_I2C_SOFT_SPEED_12,
513 CONFIG_SYS_I2C_SOFT_SLAVE_12,
514 11)
515#endif