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git01.mediatek.com / filogic / uboot / 10e4779db8ae6c2784392fa7a1f690645918662d / . / arch / arm / include / asm / arch-am33xx / hardware.h
blob: 0508b8c912abb17e37469d1d2aeb18f69ca34f2b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0+ */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]2/*
3 * hardware.h
4 *
5 * hardware specific header
6 *
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]8 */
9
10#ifndef __AM33XX_HARDWARE_H
11#define __AM33XX_HARDWARE_H
12
Matt Porter691fbe32013-03-15 10:07:06 +0000[diff] [blame]13#include <config.h>
Tom Riniee5bce42012-08-08 17:03:10 -0700[diff] [blame]14#include <asm/arch/omap.h>
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]15#ifdef CONFIG_AM33XX
16#include <asm/arch/hardware_am33xx.h>
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]17#elif defined(CONFIG_TI816X)
18#include <asm/arch/hardware_ti816x.h>
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]19#elif defined(CONFIG_TI814X)
20#include <asm/arch/hardware_ti814x.h>
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]21#elif defined(CONFIG_AM43XX)
22#include <asm/arch/hardware_am43xx.h>
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]23#endif
Tom Riniee5bce42012-08-08 17:03:10 -0700[diff] [blame]24
Matt Porter691fbe32013-03-15 10:07:06 +0000[diff] [blame]25/*
26 * Common hardware definitions
27 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]28
29/* DM Timer base addresses */
30#define DM_TIMER0_BASE 0x4802C000
31#define DM_TIMER1_BASE 0x4802E000
32#define DM_TIMER2_BASE 0x48040000
33#define DM_TIMER3_BASE 0x48042000
34#define DM_TIMER4_BASE 0x48044000
35#define DM_TIMER5_BASE 0x48046000
36#define DM_TIMER6_BASE 0x48048000
37#define DM_TIMER7_BASE 0x4804A000
38
39/* GPIO Base address */
40#define GPIO0_BASE 0x48032000
41#define GPIO1_BASE 0x4804C000
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]42
43/* BCH Error Location Module */
44#define ELM_BASE 0x48080000
45
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]46/* EMIF Base address */
47#define EMIF4_0_CFG_BASE 0x4C000000
48#define EMIF4_1_CFG_BASE 0x4D000000
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]49
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]50/* DDR Base address */
51#define DDR_CTRL_ADDR 0x44E10E04
52#define DDR_CONTROL_BASE_ADDR 0x44E11404
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]53
54/* UART */
Landheer-Cieslak, Ronald96719862017-10-25 13:46:53 +0000[diff] [blame]55#if CONFIG_CONS_INDEX == 1
56# define DEFAULT_UART_BASE UART0_BASE
57#elif CONFIG_CONS_INDEX == 2
58# define DEFAULT_UART_BASE UART1_BASE
59#elif CONFIG_CONS_INDEX == 3
60# define DEFAULT_UART_BASE UART2_BASE
61#elif CONFIG_CONS_INDEX == 4
62# define DEFAULT_UART_BASE UART3_BASE
63#elif CONFIG_CONS_INDEX == 5
64# define DEFAULT_UART_BASE UART4_BASE
65#elif CONFIG_CONS_INDEX == 6
66# define DEFAULT_UART_BASE UART5_BASE
67#endif
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]68
Ilya Yanok2ebbb862012-11-06 13:06:30 +0000[diff] [blame]69/* GPMC Base address */
70#define GPMC_BASE 0x50000000
71
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]72/* CPSW Config space */
Matt Portere24646f2013-03-15 10:07:02 +0000[diff] [blame]73#define CPSW_BASE 0x4A100000
Vaibhav Hiremath2d7da5f2012-03-08 17:15:47 +0530[diff] [blame]74
Lokesh Vutla6302e532017-05-05 12:59:10 +0530[diff] [blame]75/* Control status register */
76#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
77#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
78#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
79#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
80#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
81#define CTRL_SYSBOOT_15_14_SHIFT 22
82
83#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
84#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
85
86#define NUM_CRYSTAL_FREQ 0x4
87
Heiko Schocher0b444bb2013-08-03 07:22:49 +0200[diff] [blame]88int clk_get(int clk);
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]89#endif /* __AM33XX_HARDWARE_H */