| Calvin Johnson | 2deb8c9 | 2018-03-08 15:30:27 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2015-2016 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2017 NXP |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef _CBUS_H_ |
| 9 | #define _CBUS_H_ |
| 10 | |
| 11 | #include "cbus/emac.h" |
| 12 | #include "cbus/gpi.h" |
| 13 | #include "cbus/bmu.h" |
| 14 | #include "cbus/hif.h" |
| 15 | #include "cbus/tmu_csr.h" |
| 16 | #include "cbus/class_csr.h" |
| 17 | #include "cbus/hif_nocpy.h" |
| 18 | #include "cbus/util_csr.h" |
| 19 | |
| 20 | #define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR) |
| 21 | |
| 22 | /* PFE Control and Status Register Desciption */ |
| 23 | #define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000) |
| 24 | #define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000) |
| 25 | #define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000) |
| 26 | #define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000) |
| 27 | #define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000) |
| 28 | #define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000) |
| 29 | #define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) |
| 30 | #define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) |
| 31 | #define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000) |
| 32 | #define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000) |
| 33 | #define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000) |
| 34 | #define LMEM_SIZE 0x10000 |
| 35 | #define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE) |
| 36 | #define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000) |
| 37 | #define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) |
| 38 | #define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000) |
| 39 | #define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000) |
| 40 | #define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000) |
| 41 | |
| 42 | /* |
| 43 | * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR |
| 44 | * XXX_MEM_ACCESS_ADDR register bit definitions. |
| 45 | */ |
| 46 | /* Internal Memory Write. */ |
| 47 | #define PE_MEM_ACCESS_WRITE BIT(31) |
| 48 | /* Internal Memory Read. */ |
| 49 | #define PE_MEM_ACCESS_READ (0 << 31) |
| 50 | |
| 51 | #define PE_MEM_ACCESS_IMEM BIT(15) |
| 52 | #define PE_MEM_ACCESS_DMEM BIT(16) |
| 53 | |
| 54 | /* Byte Enables of the Internal memory access. These are interpred in BE */ |
| 55 | #define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) (((((1 << (size)) - 1) << (4 \ |
| 56 | - (offset) - (size)))\ |
| 57 | & 0xf) << 24) |
| 58 | |
| 59 | /* PFE cores states */ |
| 60 | #define CORE_DISABLE 0x00000000 |
| 61 | #define CORE_ENABLE 0x00000001 |
| 62 | #define CORE_SW_RESET 0x00000002 |
| 63 | |
| 64 | /* LMEM defines */ |
| 65 | #define LMEM_HDR_SIZE 0x0010 |
| 66 | #define LMEM_BUF_SIZE_LN2 0x7 |
| 67 | #define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2) |
| 68 | |
| 69 | /* DDR defines */ |
| 70 | #define DDR_HDR_SIZE 0x0100 |
| 71 | #define DDR_BUF_SIZE_LN2 0xb |
| 72 | #define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2) |
| 73 | |
| 74 | /* Clock generation through PLL */ |
| 75 | #define PLL_CLK_EN 1 |
| 76 | |
| 77 | #endif /* _CBUS_H_ */ |