blob: 908bdb194789282a8d433b5a83cf0b34a4458c05 [file] [log] [blame]
Phil Edworthy04a62752012-05-15 22:15:51 +00001/*
2 * Configuation settings for the Renesas RSK2+SH7269 board
3 *
4 * Copyright (C) 2012 Renesas Electronics Europe Ltd.
5 * Copyright (C) 2012 Phil Edworthy
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Phil Edworthy04a62752012-05-15 22:15:51 +00008 */
9
10#ifndef __RSK7269_H
11#define __RSK7269_H
12
Phil Edworthy04a62752012-05-15 22:15:51 +000013#define CONFIG_CPU_SH7269 1
Phil Edworthy04a62752012-05-15 22:15:51 +000014
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020015#define CONFIG_DISPLAY_BOARDINFO
16
Phil Edworthy04a62752012-05-15 22:15:51 +000017#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
18
Phil Edworthy04a62752012-05-15 22:15:51 +000019#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */
Phil Edworthy04a62752012-05-15 22:15:51 +000020
21/* Serial */
Phil Edworthy04a62752012-05-15 22:15:51 +000022#define CONFIG_CONS_SCIF7
23
24/* Memory */
25/* u-boot relocated to top 256KB of ram */
Phil Edworthy04a62752012-05-15 22:15:51 +000026#define CONFIG_SYS_SDRAM_BASE 0x0C000000
27#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
28
29#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
30#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
31#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
32#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
33#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
34
35/* NOR Flash */
36#define CONFIG_FLASH_CFI_DRIVER
37#define CONFIG_SYS_FLASH_CFI
38#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
39#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
40#define CONFIG_SYS_MAX_FLASH_BANKS 1
41#define CONFIG_SYS_MAX_FLASH_SECT 512
42
Phil Edworthy04a62752012-05-15 22:15:51 +000043#define CONFIG_ENV_OFFSET (128 * 1024)
44#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
45#define CONFIG_ENV_SECT_SIZE (64 * 1024)
46#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
47
48/* Board Clock */
49#define CONFIG_SYS_CLK_FREQ 66125000
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090050#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
51#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Phil Edworthy04a62752012-05-15 22:15:51 +000052#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
Nobuhiro Iwamatsubefb5cc2014-01-08 14:57:30 +090053#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
Phil Edworthy04a62752012-05-15 22:15:51 +000054
Phil Edworthy04a62752012-05-15 22:15:51 +000055#endif /* __RSK7269_H */