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Stelian Pop0bf5cad2008-05-08 18:52:25 +02001/*
2 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Pop0bf5cad2008-05-08 18:52:25 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9RLEK board.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stelian Pop0bf5cad2008-05-08 18:52:25 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Xu, Hong0c0fb212011-08-01 03:56:53 +000014#include <asm/hardware.h>
15
Stelian Pop0bf5cad2008-05-08 18:52:25 +020016/* ARM asynchronous clock */
Xu, Hong0c0fb212011-08-01 03:56:53 +000017#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
18#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
Stelian Pop0bf5cad2008-05-08 18:52:25 +020019
Jean-Christophe PLAGNIOL-VILLARD23164f12009-04-16 21:30:44 +020020#define CONFIG_ARCH_CPU_INIT
Xu, Hong0c0fb212011-08-01 03:56:53 +000021#define CONFIG_SKIP_LOWLEVEL_INIT
Stelian Pop0bf5cad2008-05-08 18:52:25 +020022
Xu, Hong0c0fb212011-08-01 03:56:53 +000023#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
24#define CONFIG_SETUP_MEMORY_TAGS 1
25#define CONFIG_INITRD_TAG 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020026
Xu, Hong0c0fb212011-08-01 03:56:53 +000027#define CONFIG_ATMEL_LEGACY
Stelian Pop0bf5cad2008-05-08 18:52:25 +020028
29/*
30 * Hardware drivers
31 */
Xu, Hong0c0fb212011-08-01 03:56:53 +000032
Stelian Popcea5c532008-05-08 14:52:32 +020033/* LCD */
Stelian Popcea5c532008-05-08 14:52:32 +020034#define LCD_BPP LCD_COLOR8
35#define CONFIG_LCD_LOGO 1
36#undef LCD_TEST_PATTERN
37#define CONFIG_LCD_INFO 1
38#define CONFIG_LCD_INFO_BELOW_LOGO 1
Stelian Popcea5c532008-05-08 14:52:32 +020039#define CONFIG_ATMEL_LCD 1
40#define CONFIG_ATMEL_LCD_RGB565 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000041/* Let board_init_f handle the framebuffer allocation */
42#undef CONFIG_FB_ADDR
Xu, Hong0c0fb212011-08-01 03:56:53 +000043
Stelian Pop0bf5cad2008-05-08 18:52:25 +020044/* SDRAM */
45#define CONFIG_NR_DRAM_BANKS 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000046#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
47#define CONFIG_SYS_SDRAM_SIZE 0x04000000
48
49#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang3cbbeb12017-04-18 15:28:27 +080050 (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Stelian Pop0bf5cad2008-05-08 18:52:25 +020051
Stelian Pop0bf5cad2008-05-08 18:52:25 +020052/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010053#ifdef CONFIG_CMD_NAND
54#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020055#define CONFIG_SYS_MAX_NAND_DEVICE 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000056#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010058/* our ALE is AD21 */
59#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
60/* our CLE is AD22 */
61#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
62#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
63#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
Wolfgang Denk1f797742009-07-18 21:52:24 +020064
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010065#endif
Stelian Pop0bf5cad2008-05-08 18:52:25 +020066
67/* Ethernet - not present */
68
69/* USB - not supported */
70
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Pop0bf5cad2008-05-08 18:52:25 +020072
Xu, Hong0c0fb212011-08-01 03:56:53 +000073#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Pop0bf5cad2008-05-08 18:52:25 +020075
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop0bf5cad2008-05-08 18:52:25 +020077
78/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +080079#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020080#define CONFIG_ENV_SIZE 0x4200
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +080081#define CONFIG_ENV_SECT_SIZE 0x210
82#define CONFIG_ENV_SPI_MAX_HZ 15000000
83#define CONFIG_BOOTCOMMAND "sf probe 0; " \
84 "sf read 0x22000000 0x84000 0x294000; " \
85 "bootm 0x22000000"
Stelian Pop0bf5cad2008-05-08 18:52:25 +020086
Wu, Josh7ff194f2015-02-02 17:51:01 +080087#elif CONFIG_SYS_USE_NANDFLASH
Stelian Pop0bf5cad2008-05-08 18:52:25 +020088
89/* bootstrap + u-boot + env + linux in nandflash */
Wenyou Yang3cbbeb12017-04-18 15:28:27 +080090#define CONFIG_ENV_OFFSET 0x120000
Wu, Joshf8e70d92015-02-03 11:38:30 +080091#define CONFIG_ENV_OFFSET_REDUND 0x100000
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020092#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Wu, Joshf8e70d92015-02-03 11:38:30 +080093#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x600000; " \
94 "nand read 0x21000000 0x180000 0x80000; " \
95 "bootz 0x22000000 - 0x21000000"
Stelian Pop0bf5cad2008-05-08 18:52:25 +020096
Wu, Josh7ff194f2015-02-02 17:51:01 +080097#else /* CONFIG_SYS_USE_MMC */
98
99/* bootstrap + u-boot + env + linux in mmc */
Wu, Josh7ff194f2015-02-02 17:51:01 +0800100#define CONFIG_ENV_SIZE 0x4000
101#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; " \
102 "fatload mmc 0:1 0x22000000 zImage; " \
103 "bootz 0x22000000 - 0x21000000"
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200104#endif
105
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200106/*
107 * Size of malloc() pool
108 */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000109#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200110
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200111#endif