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wdenk1fe2c702003-03-06 21:55:29 +00001/*
2 * (C) Copyright 2001, 2002, 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com`
5 * Steven Scholz, steven.scholz@imc-berlin.de
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenk1fe2c702003-03-06 21:55:29 +00008 */
9
10/*
11 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
Markus Niebel90491f22014-07-21 11:06:16 +020012 * DS1307 and DS1338/9 Real Time Clock (RTC).
wdenk1fe2c702003-03-06 21:55:29 +000013 *
14 * based on ds1337.c
15 */
16
17#include <common.h>
18#include <command.h>
Chris Packham97a3e912017-04-29 15:20:29 +120019#include <dm.h>
wdenk1fe2c702003-03-06 21:55:29 +000020#include <rtc.h>
21#include <i2c.h>
22
Chris Packham97a3e912017-04-29 15:20:29 +120023enum ds_type {
24 ds_1307,
25 ds_1337,
26 ds_1340,
27 mcp794xx,
28};
wdenk1fe2c702003-03-06 21:55:29 +000029
30/*
31 * RTC register addresses
32 */
33#define RTC_SEC_REG_ADDR 0x00
34#define RTC_MIN_REG_ADDR 0x01
35#define RTC_HR_REG_ADDR 0x02
36#define RTC_DAY_REG_ADDR 0x03
37#define RTC_DATE_REG_ADDR 0x04
38#define RTC_MON_REG_ADDR 0x05
39#define RTC_YR_REG_ADDR 0x06
40#define RTC_CTL_REG_ADDR 0x07
41
42#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
43
44#define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */
45#define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */
46#define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */
47#define RTC_CTL_BIT_OUT 0x80 /* Output Control */
48
Andy Flemingb9b8c2f2015-10-21 18:59:06 -050049/* MCP7941X-specific bits */
50#define MCP7941X_BIT_ST 0x80
51#define MCP7941X_BIT_VBATEN 0x08
52
Chris Packham97a3e912017-04-29 15:20:29 +120053#ifndef CONFIG_DM_RTC
54
55#if defined(CONFIG_CMD_DATE)
56
57/*---------------------------------------------------------------------*/
58#undef DEBUG_RTC
59
60#ifdef DEBUG_RTC
61#define DEBUGR(fmt, args...) printf(fmt, ##args)
62#else
63#define DEBUGR(fmt, args...)
64#endif
65/*---------------------------------------------------------------------*/
66
67#ifndef CONFIG_SYS_I2C_RTC_ADDR
68# define CONFIG_SYS_I2C_RTC_ADDR 0x68
69#endif
70
71#if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000)
72# error The DS1307 is specified only up to 100kHz!
73#endif
74
wdenk1fe2c702003-03-06 21:55:29 +000075static uchar rtc_read (uchar reg);
76static void rtc_write (uchar reg, uchar val);
wdenk1fe2c702003-03-06 21:55:29 +000077
78/*
79 * Get the current time from the RTC
80 */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030081int rtc_get (struct rtc_time *tmp)
wdenk1fe2c702003-03-06 21:55:29 +000082{
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030083 int rel = 0;
wdenk1fe2c702003-03-06 21:55:29 +000084 uchar sec, min, hour, mday, wday, mon, year;
85
Andy Flemingb9b8c2f2015-10-21 18:59:06 -050086#ifdef CONFIG_RTC_MCP79411
87read_rtc:
88#endif
wdenk1fe2c702003-03-06 21:55:29 +000089 sec = rtc_read (RTC_SEC_REG_ADDR);
90 min = rtc_read (RTC_MIN_REG_ADDR);
91 hour = rtc_read (RTC_HR_REG_ADDR);
92 wday = rtc_read (RTC_DAY_REG_ADDR);
93 mday = rtc_read (RTC_DATE_REG_ADDR);
94 mon = rtc_read (RTC_MON_REG_ADDR);
95 year = rtc_read (RTC_YR_REG_ADDR);
96
97 DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
98 "hr: %02x min: %02x sec: %02x\n",
99 year, mon, mday, wday, hour, min, sec);
100
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500101#ifdef CONFIG_RTC_DS1307
wdenk1fe2c702003-03-06 21:55:29 +0000102 if (sec & RTC_SEC_BIT_CH) {
103 printf ("### Warning: RTC oscillator has stopped\n");
104 /* clear the CH flag */
105 rtc_write (RTC_SEC_REG_ADDR,
106 rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300107 rel = -1;
wdenk1fe2c702003-03-06 21:55:29 +0000108 }
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500109#endif
110
111#ifdef CONFIG_RTC_MCP79411
112 /* make sure that the backup battery is enabled */
113 if (!(wday & MCP7941X_BIT_VBATEN)) {
114 rtc_write(RTC_DAY_REG_ADDR,
115 wday | MCP7941X_BIT_VBATEN);
116 }
wdenk57b2d802003-06-27 21:31:46 +0000117
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500118 /* clock halted? turn it on, so clock can tick. */
119 if (!(sec & MCP7941X_BIT_ST)) {
120 rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST);
121 printf("Started RTC\n");
122 goto read_rtc;
123 }
124#endif
125
126
wdenk1fe2c702003-03-06 21:55:29 +0000127 tmp->tm_sec = bcd2bin (sec & 0x7F);
128 tmp->tm_min = bcd2bin (min & 0x7F);
129 tmp->tm_hour = bcd2bin (hour & 0x3F);
130 tmp->tm_mday = bcd2bin (mday & 0x3F);
131 tmp->tm_mon = bcd2bin (mon & 0x1F);
132 tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
133 tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
134 tmp->tm_yday = 0;
135 tmp->tm_isdst= 0;
136
137 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
138 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
139 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300140
141 return rel;
wdenk1fe2c702003-03-06 21:55:29 +0000142}
143
144
145/*
146 * Set the RTC
147 */
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200148int rtc_set (struct rtc_time *tmp)
wdenk1fe2c702003-03-06 21:55:29 +0000149{
150 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
151 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
152 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
153
154 if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
155 printf("WARNING: year should be between 1970 and 2069!\n");
wdenk57b2d802003-06-27 21:31:46 +0000156
wdenk1fe2c702003-03-06 21:55:29 +0000157 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
158 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500159#ifdef CONFIG_RTC_MCP79411
160 rtc_write (RTC_DAY_REG_ADDR,
161 bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN);
162#else
wdenk1fe2c702003-03-06 21:55:29 +0000163 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500164#endif
wdenk1fe2c702003-03-06 21:55:29 +0000165 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
166 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
167 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500168#ifdef CONFIG_RTC_MCP79411
169 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST);
170#else
wdenk1fe2c702003-03-06 21:55:29 +0000171 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500172#endif
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200173
174 return 0;
wdenk1fe2c702003-03-06 21:55:29 +0000175}
176
177
178/*
wdenk57b2d802003-06-27 21:31:46 +0000179 * Reset the RTC. We setting the date back to 1970-01-01.
180 * We also enable the oscillator output on the SQW/OUT pin and program
wdenk1fe2c702003-03-06 21:55:29 +0000181 * it for 32,768 Hz output. Note that according to the datasheet, turning
182 * on the square wave output increases the current drain on the backup
183 * battery to something between 480nA and 800nA.
184 */
185void rtc_reset (void)
186{
wdenk1fe2c702003-03-06 21:55:29 +0000187 rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
188 rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0);
wdenk1fe2c702003-03-06 21:55:29 +0000189}
190
191
192/*
193 * Helper functions
194 */
195
196static
197uchar rtc_read (uchar reg)
198{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
wdenk1fe2c702003-03-06 21:55:29 +0000200}
201
202
203static void rtc_write (uchar reg, uchar val)
204{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
wdenk1fe2c702003-03-06 21:55:29 +0000206}
Chris Packham97a3e912017-04-29 15:20:29 +1200207
208#endif /* CONFIG_CMD_DATE*/
209
210#endif /* !CONFIG_DM_RTC */
211
212#ifdef CONFIG_DM_RTC
213static int ds1307_rtc_set(struct udevice *dev, const struct rtc_time *tm)
214{
215 int ret;
216 uchar buf[7];
217 enum ds_type type = dev_get_driver_data(dev);
218
219 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
220 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
221 tm->tm_hour, tm->tm_min, tm->tm_sec);
222
223 if (tm->tm_year < 1970 || tm->tm_year > 2069)
224 printf("WARNING: year should be between 1970 and 2069!\n");
225
226 buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100);
227 buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon);
228 buf[RTC_DAY_REG_ADDR] = bin2bcd(tm->tm_wday + 1);
229 buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday);
230 buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour);
231 buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min);
232 buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec);
233
234 if (type == mcp794xx) {
235 buf[RTC_DAY_REG_ADDR] |= MCP7941X_BIT_VBATEN;
236 buf[RTC_SEC_REG_ADDR] |= MCP7941X_BIT_ST;
237 }
238
239 ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
240 if (ret < 0)
241 return ret;
242
243 return 0;
244}
245
246static int ds1307_rtc_get(struct udevice *dev, struct rtc_time *tm)
247{
248 int ret;
249 uchar buf[7];
250 enum ds_type type = dev_get_driver_data(dev);
251
252read_rtc:
253 ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
254 if (ret < 0)
255 return ret;
256
257 if (type == ds_1307) {
258 if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
259 printf("### Warning: RTC oscillator has stopped\n");
260 /* clear the CH flag */
261 buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
262 dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
263 buf[RTC_SEC_REG_ADDR]);
264 return -1;
265 }
266 }
267
268 if (type == mcp794xx) {
269 /* make sure that the backup battery is enabled */
270 if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) {
271 dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR,
272 buf[RTC_DAY_REG_ADDR] |
273 MCP7941X_BIT_VBATEN);
274 }
275
276 /* clock halted? turn it on, so clock can tick. */
277 if (!(buf[RTC_SEC_REG_ADDR] & MCP7941X_BIT_ST)) {
278 dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
279 MCP7941X_BIT_ST);
280 printf("Started RTC\n");
281 goto read_rtc;
282 }
283 }
284
285 tm->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
286 tm->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
287 tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
288 tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
289 tm->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
290 tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) +
291 (bcd2bin(buf[RTC_YR_REG_ADDR]) >= 70 ?
292 1900 : 2000);
293 tm->tm_wday = bcd2bin((buf[RTC_DAY_REG_ADDR] - 1) & 0x07);
294 tm->tm_yday = 0;
295 tm->tm_isdst = 0;
296
297 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
298 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
299 tm->tm_hour, tm->tm_min, tm->tm_sec);
300
301 return 0;
302}
303
304static int ds1307_rtc_reset(struct udevice *dev)
305{
306 int ret;
Chris Packham97a3e912017-04-29 15:20:29 +1200307
308 /* clear Clock Halt */
309 ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00);
310 if (ret < 0)
311 return ret;
312 ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
313 RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 |
314 RTC_CTL_BIT_RS0);
315 if (ret < 0)
316 return ret;
317
Chris Packham97a3e912017-04-29 15:20:29 +1200318 return 0;
319}
320
321static int ds1307_probe(struct udevice *dev)
322{
323 i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
324 DM_I2C_CHIP_WR_ADDRESS);
325
326 return 0;
327}
328
329static const struct rtc_ops ds1307_rtc_ops = {
330 .get = ds1307_rtc_get,
331 .set = ds1307_rtc_set,
332 .reset = ds1307_rtc_reset,
333};
334
335static const struct udevice_id ds1307_rtc_ids[] = {
336 { .compatible = "dallas,ds1307", .data = ds_1307 },
337 { .compatible = "dallas,ds1337", .data = ds_1337 },
338 { .compatible = "dallas,ds1340", .data = ds_1340 },
339 { .compatible = "microchip,mcp7941x", .data = mcp794xx },
340 { }
341};
342
343U_BOOT_DRIVER(rtc_ds1307) = {
344 .name = "rtc-ds1307",
345 .id = UCLASS_RTC,
346 .probe = ds1307_probe,
347 .of_match = ds1307_rtc_ids,
348 .ops = &ds1307_rtc_ops,
349};
350#endif /* CONFIG_DM_RTC */