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git01.mediatek.com / filogic / uboot / cb2accdbb2ce82afdb6e915bbee41ec5cce595ee / . / board / keymile / common / common.h
blob: 81a0af0c3c9a0320254447894617412417435d39 [file] [log] [blame]
Heiko Schocherd19a6ec2008-11-21 08:29:40 +0100[diff] [blame]1/*
2 * (C) Copyright 2008
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocherd19a6ec2008-11-21 08:29:40 +0100[diff] [blame]6 */
7
8#ifndef __KEYMILE_COMMON_H
9#define __KEYMILE_COMMON_H
10
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]11#define WRG_RESET 0x80
12#define H_OPORTS_14 0x40
13#define WRG_LED 0x02
14#define WRL_BOOT 0x01
15
Stefan Biglerabcd23c2012-05-04 10:55:55 +0200[diff] [blame]16#define OPRTL_XBUFENA 0x20
17
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]18#define H_OPORTS_SCC4_ENA 0x10
19#define H_OPORTS_SCC4_FD_ENA 0x04
20#define H_OPORTS_FCC1_PW_DWN 0x01
21
22#define PIGGY_PRESENT 0x80
23
24struct km_bec_fpga {
25 unsigned char id;
26 unsigned char rev;
27 unsigned char oprth;
28 unsigned char oprtl;
29 unsigned char res1[3];
30 unsigned char bprth;
31 unsigned char bprtl;
Thomas Herzmann94fbf522012-05-04 10:55:56 +0200[diff] [blame]32 unsigned char gprt3;
33 unsigned char gprt2;
34 unsigned char gprt1;
35 unsigned char gprt0;
36 unsigned char res2[2];
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]37 unsigned char prst;
38 unsigned char res3[0xfff0];
39 unsigned char pgy_id;
40 unsigned char pgy_rev;
41 unsigned char pgy_outputs;
42 unsigned char pgy_eth;
43};
44
Huber, Andreas49adfa82011-05-02 22:56:54 +0000[diff] [blame]45#define BFTICU_DIPSWITCH_MASK 0x0f
46
47/*
48 * BFTICU FPGA iomap
49 * BFTICU is used on mgcoge and mgocge3ne
50 */
51struct bfticu_iomap {
52 u8 xi_ena; /* General defect enable */
53 u8 pack1[3];
54 u8 en_csn;
55 u8 pack2;
56 u8 safe_mem;
57 u8 pack3;
58 u8 id;
59 u8 pack4;
60 u8 rev;
61 u8 build;
62 u8 p_frc;
63 u8 p_msk;
64 u8 pack5[2];
65 u8 xg_int;
66 u8 pack6[15];
67 u8 s_conf;
68 u8 pack7;
69 u8 dmx_conf12;
70 u8 pack8;
71 u8 s_clkslv;
72 u8 pack9[11];
73 u8 d_conf;
74 u8 d_mask_ca;
75 u8 d_pll_del;
76 u8 pack10[16];
77 u8 t_conf_ca;
78 u8 t_mask_ca;
79 u8 pack11[13];
80 u8 m_def0;
81 u8 m_def1;
82 u8 m_def2;
83 u8 m_def3;
84 u8 m_def4;
85 u8 m_def5;
86 u8 m_def_trap0;
87 u8 m_def_trap1;
88 u8 m_def_trap2;
89 u8 m_def_trap3;
90 u8 m_def_trap4;
91 u8 m_def_trap5;
92 u8 m_mask_def0;
93 u8 m_mask_def1;
94 u8 m_mask_def2;
95 u8 m_mask_def3;
96 u8 m_mask_def4;
97 u8 m_mask_def5;
98 u8 m_def_mask0;
99 u8 m_def_mask1;
100 u8 m_def_mask2;
101 u8 m_def_mask3;
102 u8 m_def_mask4;
103 u8 m_def_mask5;
104 u8 m_def_pri;
105 u8 pack12[11];
106 u8 hw_status;
107 u8 pack13;
108 u8 hw_control1;
109 u8 hw_control2;
110 u8 hw_control3;
111 u8 pack14[7];
112 u8 led_on; /* Leds */
113 u8 pack15;
114 u8 sfp_control; /* SFP modules */
115 u8 pack16;
116 u8 alarm_control; /* Alarm output */
117 u8 pack17;
118 u8 icps; /* ICN clock pulse shaping */
119 u8 mswitch; /* Read mode switch */
120 u8 pack18[6];
121 u8 pb_dbug;
122};
123
Heiko Schocherb7aa50f2011-01-06 10:25:26 +0100[diff] [blame]124#if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
125#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0
126#endif
127
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]128int ethernet_present(void);
Valentin Longchamp876f7a92015-02-10 17:10:18 +0100[diff] [blame]129int ivm_read_eeprom(unsigned char *buf, int len);
Valentin Longchamp123c5e42015-02-10 17:10:13 +0100[diff] [blame]130int ivm_analyze_eeprom(unsigned char *buf, int len);
Heiko Schocherd19a6ec2008-11-21 08:29:40 +0100[diff] [blame]131
Valentin Longchamp6633fed2012-07-05 05:05:05 +0000[diff] [blame]132int trigger_fpga_config(void);
133int wait_for_fpga_config(void);
134int fpga_reset(void);
135int toggle_eeprom_spi_bus(void);
136
Holger Bruncke2d22392015-11-17 10:53:26 +0100[diff] [blame]137int get_testpin(void);
138
Heiko Schochercfc58042010-04-26 13:07:28 +0200[diff] [blame]139int set_km_env(void);
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]140
Holger Brunck015a60f2011-09-14 10:54:12 +0200[diff] [blame]141#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
142#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
143
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]144int i2c_soft_read_pin(void);
Holger Brunckbf20a882011-06-05 22:22:18 +0000[diff] [blame]145int i2c_make_abort(void);
Heiko Schocherd19a6ec2008-11-21 08:29:40 +0100[diff] [blame]146#endif /* __KEYMILE_COMMON_H */