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git01.mediatek.com / filogic / uboot / cb2accdbb2ce82afdb6e915bbee41ec5cce595ee / . / arch / powerpc / include / asm / fsl_pamu.h
blob: 93a7cae972a0b32d6e2b1fd046361e8e33132e41 [file] [log] [blame]
Aneesh Bansal4b636c32016-01-22 17:05:59 +0530[diff] [blame]1/*
2 * Copyright 2012-2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __PAMU_H
8#define __PAMU_H
9
10#define CONFIG_NUM_PAMU 16
11#define NUM_PPAACT_ENTRIES 512
12#define NUM_SPAACT_ENTRIES 256
13
14/* PAMU_OFFSET to the next pamu space in ccsr */
15#define PAMU_OFFSET 0x1000
16
17#define PAMU_TABLE_ALIGNMENT 0x00001000
18
19#define PAMU_PAGE_SHIFT 12
20#define PAMU_PAGE_SIZE 4096U
21
22#define PAACE_M_COHERENCE_REQ 0x01
23
24#define PAACE_DA_HOST_CR 0x80
25#define PAACE_DA_HOST_CR_SHIFT 7
26
27#define PAACE_AF_PT 0x00000002
28#define PAACE_AF_PT_SHIFT 1
29
30#define PAACE_PT_PRIMARY 0x0
31#define PAACE_PT_SECONDARY 0x1
32
33#define PPAACE_AF_WBAL 0xfffff000
34#define PPAACE_AF_WBAL_SHIFT 12
35
36#define OME_NUMBER_ENTRIES 16 /* based on P4080 2.0 silicon plan */
37
38#define PAACE_IA_CID 0x00FF0000
39#define PAACE_IA_CID_SHIFT 16
40#define PAACE_IA_WCE 0x000000F0
41#define PAACE_IA_WCE_SHIFT 4
42#define PAACE_IA_ATM 0x0000000C
43#define PAACE_IA_ATM_SHIFT 2
44#define PAACE_IA_OTM 0x00000003
45#define PAACE_IA_OTM_SHIFT 0
46
47#define PAACE_OTM_NO_XLATE 0x00
48#define PAACE_OTM_IMMEDIATE 0x01
49#define PAACE_OTM_INDEXED 0x02
50#define PAACE_OTM_RESERVED 0x03
51#define PAACE_ATM_NO_XLATE 0x00
52#define PAACE_ATM_WINDOW_XLATE 0x01
53#define PAACE_ATM_PAGE_XLATE 0x02
54#define PAACE_ATM_WIN_PG_XLATE \
55 (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
56#define PAACE_WIN_TWBAL 0xfffff000
57#define PAACE_WIN_TWBAL_SHIFT 12
58#define PAACE_WIN_SWSE 0x00000fc0
59#define PAACE_WIN_SWSE_SHIFT 6
60
61#define PAACE_AF_AP 0x00000018
62#define PAACE_AF_AP_SHIFT 3
63#define PAACE_AF_DD 0x00000004
64#define PAACE_AF_DD_SHIFT 2
65#define PAACE_AF_PT 0x00000002
66#define PAACE_AF_PT_SHIFT 1
67#define PAACE_AF_V 0x00000001
68#define PAACE_AF_V_SHIFT 0
69#define PPAACE_AF_WSE 0x00000fc0
70#define PPAACE_AF_WSE_SHIFT 6
71#define PPAACE_AF_MW 0x00000020
72#define PPAACE_AF_MW_SHIFT 5
73
74#define PAACE_AP_PERMS_DENIED 0x0
75#define PAACE_AP_PERMS_QUERY 0x1
76#define PAACE_AP_PERMS_UPDATE 0x2
77#define PAACE_AP_PERMS_ALL 0x3
78
79#define SPAACE_AF_LIODN 0xffff0000
80#define SPAACE_AF_LIODN_SHIFT 16
81#define PAACE_V_VALID 0x1
82
83#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << \
84 (m##_SHIFT)) & (m)))
85#define get_bf(v, m) (((v) & (m)) >> (m##_SHIFT))
86
87#define DEFAULT_NUM_SUBWINDOWS 128
88#define PAMU_PCR_OFFSET 0xc10
89#define PAMU_PCR_PE 0x40000000
90
91struct pamu_addr_tbl {
92 phys_addr_t start_addr[10];
93 phys_addr_t end_addr[10];
94 phys_size_t size[10];
95};
96
97struct paace {
98 /* PAACE Offset 0x00 */
99 uint32_t wbah; /* only valid for Primary PAACE */
100 uint32_t addr_bitfields; /* See P/S PAACE_AF_* */
101
102 /* PAACE Offset 0x08 */
103 /* Interpretation of first 32 bits dependent on DD above */
104 union {
105 struct {
106 /* Destination ID, see PAACE_DID_* defines */
107 uint8_t did;
108 /* Partition ID */
109 uint8_t pid;
110 /* Snoop ID */
111 uint8_t snpid;
112 /* coherency_required : 1 reserved : 7 */
113 uint8_t coherency_required; /* See PAACE_DA_* */
114 } to_host;
115 struct {
116 /* Destination ID, see PAACE_DID_* defines */
117 uint8_t did;
118 uint8_t reserved1;
119 uint16_t reserved2;
120 } to_io;
121 } domain_attr;
122
123 /* Implementation attributes + window count + address & operation
124 * translation modes
125 */
126 uint32_t impl_attr; /* See PAACE_IA_* */
127
128 /* PAACE Offset 0x10 */
129 /* Translated window base address */
130 uint32_t twbah;
131 uint32_t win_bitfields; /* See PAACE_WIN_* */
132
133 /* PAACE Offset 0x18 */
134 /* first secondary paace entry */
135 uint32_t fspi; /* only valid for Primary PAACE */
136 union {
137 struct {
138 uint8_t ioea;
139 uint8_t moea;
140 uint8_t ioeb;
141 uint8_t moeb;
142 } immed_ot;
143 struct {
144 uint16_t reserved;
145 uint16_t omi;
146 } index_ot;
147 } op_encode;
148
149 /* PAACE Offset 0x20 */
150 uint32_t reserved1[2]; /* not currently implemented */
151
152 /* PAACE Offset 0x28 */
153 uint32_t reserved2[2]; /* not currently implemented */
154
155 /* PAACE Offset 0x30 */
156 uint32_t reserved3[2]; /* not currently implemented */
157
158 /* PAACE Offset 0x38 */
159 uint32_t reserved4[2]; /* not currently implemented */
160
161};
162
163int pamu_init(void);
164void pamu_enable(void);
165void pamu_disable(void);
166int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn);
167int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s);
168
169#endif