| Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Qualcomm APQ8096 sysmap |
| 3 | * |
| 4 | * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | #ifndef _MACH_SYSMAP_APQ8096_H |
| 9 | #define _MACH_SYSMAP_APQ8096_H |
| 10 | |
| 11 | #define TLMM_BASE_ADDR (0x1010000) |
| 12 | |
| 13 | /* Strength (sdc1) */ |
| 14 | #define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) |
| 15 | |
| 16 | /* Clocks: (from CLK_CTL_BASE) */ |
| 17 | #define GPLL0_STATUS (0x0000) |
| 18 | #define APCS_GPLL_ENA_VOTE (0x52000) |
| 19 | |
| 20 | #define SDCC2_BCR (0x14000) /* block reset */ |
| 21 | #define SDCC2_APPS_CBCR (0x14004) /* branch control */ |
| 22 | #define SDCC2_AHB_CBCR (0x14008) |
| 23 | #define SDCC2_CMD_RCGR (0x14010) |
| 24 | #define SDCC2_CFG_RCGR (0x14014) |
| 25 | #define SDCC2_M (0x14018) |
| 26 | #define SDCC2_N (0x1401C) |
| 27 | #define SDCC2_D (0x14020) |
| 28 | |
| 29 | #endif |