| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 |
| 3 | * Toradex, Inc. |
| 4 | * |
| 5 | * Authors: Stefan Agner |
| 6 | * Sanchayan Maity |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ASM_ARCH_VF610_DDRMC_H |
| 12 | #define __ASM_ARCH_VF610_DDRMC_H |
| 13 | |
| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 14 | struct ddr3_jedec_timings { |
| 15 | u8 tinit; |
| 16 | u32 trst_pwron; |
| 17 | u32 cke_inactive; |
| 18 | u8 wrlat; |
| 19 | u8 caslat_lin; |
| 20 | u8 trc; |
| 21 | u8 trrd; |
| 22 | u8 tccd; |
| Albert ARIBAUD \\(3ADEV\\) | 25ac8ce | 2015-09-21 22:43:37 +0200 | [diff] [blame] | 23 | u8 tbst_int_interval; |
| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 24 | u8 tfaw; |
| 25 | u8 trp; |
| 26 | u8 twtr; |
| 27 | u8 tras_min; |
| 28 | u8 tmrd; |
| 29 | u8 trtp; |
| 30 | u32 tras_max; |
| 31 | u8 tmod; |
| 32 | u8 tckesr; |
| 33 | u8 tcke; |
| 34 | u8 trcd_int; |
| Albert ARIBAUD \\(3ADEV\\) | 25ac8ce | 2015-09-21 22:43:37 +0200 | [diff] [blame] | 35 | u8 tras_lockout; |
| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 36 | u8 tdal; |
| Albert ARIBAUD \\(3ADEV\\) | 25ac8ce | 2015-09-21 22:43:37 +0200 | [diff] [blame] | 37 | u8 bstlen; |
| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 38 | u16 tdll; |
| 39 | u8 trp_ab; |
| 40 | u16 tref; |
| 41 | u8 trfc; |
| Albert ARIBAUD \\(3ADEV\\) | 25ac8ce | 2015-09-21 22:43:37 +0200 | [diff] [blame] | 42 | u16 tref_int; |
| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 43 | u8 tpdex; |
| 44 | u8 txpdll; |
| 45 | u8 txsnr; |
| 46 | u16 txsr; |
| 47 | u8 cksrx; |
| 48 | u8 cksre; |
| Albert ARIBAUD \\(3ADEV\\) | 25ac8ce | 2015-09-21 22:43:37 +0200 | [diff] [blame] | 49 | u8 freq_chg_en; |
| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 50 | u16 zqcl; |
| 51 | u16 zqinit; |
| 52 | u8 zqcs; |
| 53 | u8 ref_per_zq; |
| Albert ARIBAUD \\(3ADEV\\) | 25ac8ce | 2015-09-21 22:43:37 +0200 | [diff] [blame] | 54 | u8 zqcs_rotate; |
| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 55 | u8 aprebit; |
| Albert ARIBAUD \\(3ADEV\\) | 25ac8ce | 2015-09-21 22:43:37 +0200 | [diff] [blame] | 56 | u8 cmd_age_cnt; |
| 57 | u8 age_cnt; |
| 58 | u8 q_fullness; |
| 59 | u8 odt_rd_mapcs0; |
| 60 | u8 odt_wr_mapcs0; |
| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 61 | u8 wlmrd; |
| 62 | u8 wldqsen; |
| 63 | }; |
| 64 | |
| Albert ARIBAUD \\(3ADEV\\) | 25ac8ce | 2015-09-21 22:43:37 +0200 | [diff] [blame] | 65 | struct ddrmc_cr_setting { |
| 66 | u32 setting; |
| 67 | int cr_rnum; /* CR register ; -1 for last entry */ |
| 68 | }; |
| 69 | |
| 70 | struct ddrmc_phy_setting { |
| 71 | u32 setting; |
| 72 | int phy_rnum; /* PHY register ; -1 for last entry */ |
| 73 | }; |
| 74 | |
| 75 | void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count); |
| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 76 | void ddrmc_phy_init(void); |
| 77 | void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, |
| Albert ARIBAUD \\(3ADEV\\) | 25ac8ce | 2015-09-21 22:43:37 +0200 | [diff] [blame] | 78 | struct ddrmc_cr_setting *board_cr_settings, |
| 79 | struct ddrmc_phy_setting *board_phy_settings, |
| 80 | int col_diff, int row_diff); |
| Sanchayan Maity | e3a76e2 | 2015-04-15 16:24:22 +0530 | [diff] [blame] | 81 | |
| 82 | #endif |