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git01.mediatek.com / filogic / uboot / 10bdc719c1b0405ff8d27ac70ffd8bfa9de3403c / . / arch / sh / include / asm / cpu_sh7757.h
blob: a64602d8b8b679dfd0e83fbc257407b7e533da56 [file] [log] [blame]
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]1/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]5 */
6
7#ifndef _ASM_CPU_SH7757_H_
8#define _ASM_CPU_SH7757_H_
9
10#define CCR 0xFF00001C
11#define WTCNT 0xFFCC0000
12#define CCR_CACHE_INIT 0x0000090b
13#define CACHE_OC_NUM_WAYS 1
14
15#ifndef __ASSEMBLY__ /* put C only stuff in this section */
16/* MMU */
17struct mmu_regs {
18 unsigned int reserved[4];
19 unsigned int mmucr;
20};
21#define MMU_BASE ((struct mmu_regs *)0xff000000)
22
23/* Watchdog */
24#define WTCSR0 0xffcc0002
25#define WRSTCSR_R 0xffcc0003
26#define WRSTCSR_W 0xffcc0002
27#define WTCSR_PREFIX 0xa500
28#define WRSTCSR_PREFIX 0x6900
29#define WRSTCSR_WOVF_PREFIX 0x9600
30
31/* SCIF */
32#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
33#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
34#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
35
36/* SerMux */
37#define SMR0 0xfe470000
38
39/* TMU0 */
Nobuhiro Iwamatsue763f1a2012-08-21 13:14:46 +0900[diff] [blame]40#define TMU_BASE 0xFE430000
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]41
42/* ETHER, GETHER MAC address */
43struct ether_mac_regs {
44 unsigned int reserved[114];
45 unsigned int mahr;
46 unsigned int reserved2;
47 unsigned int malr;
48};
49#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
50#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
51#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
52#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
53
54/* GETHER */
55struct gether_control_regs {
56 unsigned int gbecont;
57};
58#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
59#define GBECONT_RMII1 0x00020000
60#define GBECONT_RMII0 0x00010000
61
62/* USB0/1 */
63struct usb_common_regs {
64 unsigned short reserved[129];
65 unsigned short suspmode;
66};
67#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
68#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
69
70struct usb0_phy_regs {
71 unsigned short reset;
72 unsigned short reserved[4];
73 unsigned short portsel;
74};
75#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
76
77struct usb1_port_regs {
78 unsigned int port1sel;
79 unsigned int reserved;
80 unsigned int usb1intsts;
81};
82#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
83
84struct usb1_alignment_regs {
85 unsigned int ehcidatac; /* 0xfe4fe018 */
86 unsigned int reserved[63];
87 unsigned int ohcidatac;
88};
89#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
90
91/* GCTRL, GRA */
92struct gctrl_regs {
93 unsigned int wprotect;
94 unsigned int gplldiv;
95 unsigned int gracr2; /* GRA */
96 unsigned int gracr3; /* GRA */
97 unsigned int reserved[4];
98 unsigned int fcntcr1;
99 unsigned int fcntcr2;
100 unsigned int reserved2[2];
101 unsigned int gpll1div;
102 unsigned int vcompsel;
103 unsigned int reserved3[62];
104 unsigned int fdlmon;
105 unsigned int reserved4[2];
106 unsigned int flcrmon;
107 unsigned int reserved5[944];
108 unsigned int spibootcan;
109};
110#define GCTRL_BASE ((struct gctrl_regs *)0xffc10000)
111
112/* PCIe setup */
113struct pcie_setup_regs {
114 unsigned int pbictl0;
115 unsigned int gradevctl;
116 unsigned int reserved[2];
117 unsigned int bmcinf[6];
118 unsigned int reserved2[118];
119 unsigned int idset[2];
120 unsigned int subidset;
121 unsigned int reserved3[2];
122 unsigned int linkconfset[4];
123 unsigned int trsid;
124 unsigned int reserved4[6];
125 unsigned int toutset;
126 unsigned int reserved5[7];
127 unsigned int lad0;
128 unsigned int ladmsk0;
129 unsigned int lad1;
130 unsigned int ladmsk1;
131 unsigned int lad2;
132 unsigned int ladmsk2;
133 unsigned int lad3;
134 unsigned int ladmsk3;
135 unsigned int lad4;
136 unsigned int ladmsk4;
137 unsigned int lad5;
138 unsigned int ladmsk5;
139 unsigned int reserved6[94];
140 unsigned int vdmrxvid[2];
141 unsigned int reserved7;
142 unsigned int pbiintfr;
143 unsigned int pbiinten;
144 unsigned int msimap;
145 unsigned int barmap;
146 unsigned int baracsize;
147 unsigned int advserest;
148 unsigned int pbictl3;
149 unsigned int reserved8[8];
150 unsigned int pbictl1;
151 unsigned int scratch0;
152 unsigned int reserved9[6];
153 unsigned int pbictl2;
154 unsigned int reserved10;
155 unsigned int pbirev;
156};
157#define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000)
158
159struct pcie_system_bus_regs {
160 unsigned int reserved[3];
161 unsigned int endictl0;
162 unsigned int endictl1;
163};
164#define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600)
165
166
167/* PCIe-Bridge */
168struct pciebrg_regs {
169 unsigned short ctrl_h8s;
170 unsigned short reserved[7];
171 unsigned short cp_addr;
172 unsigned short reserved2;
173 unsigned short cp_data;
174 unsigned short reserved3;
175 unsigned short cp_ctrl;
176};
177#define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000)
178
179/* CPU version */
180#define CCN_PRR 0xff000044
181#define prr_mask(_val) ((_val >> 4) & 0xff)
182#define PRR_SH7757_B0 0x10
183#define PRR_SH7757_C0 0x11
184
185#define is_sh7757_b0(_val) \
186({ \
187 int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \
188 __ret; \
189})
190#endif /* ifndef __ASSEMBLY__ */
191
192#endif /* _ASM_CPU_SH7757_H_ */