Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014 Samsung Electronics |
| 4 | * Przemyslaw Marczak <p.marczak@samsung.com> |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame^] | 8 | #include <log.h> |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 9 | #include <asm/arch/pinmux.h> |
| 10 | #include <asm/arch/power.h> |
| 11 | #include <asm/arch/clock.h> |
| 12 | #include <asm/arch/gpio.h> |
| 13 | #include <asm/gpio.h> |
| 14 | #include <asm/arch/cpu.h> |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 15 | #include <dm.h> |
Simon Glass | 0af6e2d | 2019-08-01 09:46:52 -0600 | [diff] [blame] | 16 | #include <env.h> |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 17 | #include <power/pmic.h> |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 18 | #include <power/regulator.h> |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 19 | #include <power/max77686_pmic.h> |
| 20 | #include <errno.h> |
Inha Song | ae731ec | 2015-02-17 12:24:12 +0100 | [diff] [blame] | 21 | #include <mmc.h> |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 22 | #include <usb.h> |
Marek Vasut | f1be9cb | 2015-12-04 02:51:20 +0100 | [diff] [blame] | 23 | #include <usb/dwc2_udc.h> |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 24 | #include <samsung/misc.h> |
| 25 | #include "setup.h" |
| 26 | |
| 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
| 29 | #ifdef CONFIG_BOARD_TYPES |
| 30 | /* Odroid board types */ |
| 31 | enum { |
| 32 | ODROID_TYPE_U3, |
| 33 | ODROID_TYPE_X2, |
| 34 | ODROID_TYPES, |
| 35 | }; |
| 36 | |
| 37 | void set_board_type(void) |
| 38 | { |
| 39 | /* Set GPA1 pin 1 to HI - enable XCL205 output */ |
| 40 | writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON); |
| 41 | writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4); |
| 42 | writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8); |
| 43 | writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc); |
| 44 | |
| 45 | /* Set GPC1 pin 2 to IN - check XCL205 output state */ |
| 46 | writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON); |
| 47 | writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8); |
| 48 | |
| 49 | /* XCL205 - needs some latch time */ |
| 50 | sdelay(200000); |
| 51 | |
| 52 | /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */ |
| 53 | if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN)) |
| 54 | gd->board_type = ODROID_TYPE_X2; |
| 55 | else |
| 56 | gd->board_type = ODROID_TYPE_U3; |
| 57 | } |
| 58 | |
Krzysztof Kozlowski | 36476ee | 2019-03-06 19:37:51 +0100 | [diff] [blame] | 59 | void set_board_revision(void) |
| 60 | { |
| 61 | /* |
| 62 | * Revision already set by set_board_type() because it can be |
| 63 | * executed early. |
| 64 | */ |
| 65 | } |
| 66 | |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 67 | const char *get_board_type(void) |
| 68 | { |
| 69 | const char *board_type[] = {"u3", "x2"}; |
| 70 | |
| 71 | return board_type[gd->board_type]; |
| 72 | } |
| 73 | #endif |
| 74 | |
| 75 | #ifdef CONFIG_SET_DFU_ALT_INFO |
Inha Song | ae731ec | 2015-02-17 12:24:12 +0100 | [diff] [blame] | 76 | char *get_dfu_alt_system(char *interface, char *devstr) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 77 | { |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 78 | return env_get("dfu_alt_system"); |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 79 | } |
| 80 | |
Inha Song | ae731ec | 2015-02-17 12:24:12 +0100 | [diff] [blame] | 81 | char *get_dfu_alt_boot(char *interface, char *devstr) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 82 | { |
Inha Song | ae731ec | 2015-02-17 12:24:12 +0100 | [diff] [blame] | 83 | struct mmc *mmc; |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 84 | char *alt_boot; |
Inha Song | ae731ec | 2015-02-17 12:24:12 +0100 | [diff] [blame] | 85 | int dev_num; |
| 86 | |
| 87 | dev_num = simple_strtoul(devstr, NULL, 10); |
| 88 | |
| 89 | mmc = find_mmc_device(dev_num); |
| 90 | if (!mmc) |
| 91 | return NULL; |
| 92 | |
| 93 | if (mmc_init(mmc)) |
| 94 | return NULL; |
| 95 | |
| 96 | alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD : |
| 97 | CONFIG_DFU_ALT_BOOT_EMMC; |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 98 | |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 99 | return alt_boot; |
| 100 | } |
| 101 | #endif |
| 102 | |
| 103 | static void board_clock_init(void) |
| 104 | { |
| 105 | unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; |
| 106 | struct exynos4x12_clock *clk = (struct exynos4x12_clock *) |
| 107 | samsung_get_base_clock(); |
| 108 | |
| 109 | /* |
| 110 | * CMU_CPU clocks src to MPLL |
| 111 | * Bit values: 0 ; 1 |
| 112 | * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL |
| 113 | * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL |
| 114 | * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C |
| 115 | * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL |
| 116 | */ |
| 117 | clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) | |
| 118 | MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1); |
| 119 | set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) | |
| 120 | MUX_MPLL_USER_SEL_C(1); |
| 121 | |
| 122 | clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); |
| 123 | |
| 124 | /* Wait for mux change */ |
| 125 | while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) |
| 126 | continue; |
| 127 | |
| 128 | /* Set APLL to 1000MHz */ |
| 129 | clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); |
| 130 | set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); |
| 131 | |
| 132 | clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); |
| 133 | |
| 134 | /* Wait for PLL to be locked */ |
| 135 | while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) |
| 136 | continue; |
| 137 | |
| 138 | /* Set CMU_CPU clocks src to APLL */ |
| 139 | set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) | |
| 140 | MUX_MPLL_USER_SEL_C(1); |
| 141 | clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); |
| 142 | |
| 143 | /* Wait for mux change */ |
| 144 | while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) |
| 145 | continue; |
| 146 | |
| 147 | set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) | |
| 148 | PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) | |
| 149 | APLL_RATIO(0) | CORE2_RATIO(0); |
| 150 | /* |
| 151 | * Set dividers for MOUTcore = 1000 MHz |
| 152 | * coreout = MOUT / (ratio + 1) = 1000 MHz (0) |
| 153 | * corem0 = armclk / (ratio + 1) = 333 MHz (2) |
| 154 | * corem1 = armclk / (ratio + 1) = 166 MHz (5) |
| 155 | * periph = armclk / (ratio + 1) = 1000 MHz (0) |
| 156 | * atbout = MOUT / (ratio + 1) = 200 MHz (4) |
| 157 | * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) |
| 158 | * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) |
| 159 | * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) |
| 160 | */ |
| 161 | clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | |
| 162 | PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) | |
| 163 | APLL_RATIO(7) | CORE2_RATIO(7); |
| 164 | |
| 165 | clrsetbits_le32(&clk->div_cpu0, clr, set); |
| 166 | |
| 167 | /* Wait for divider ready status */ |
| 168 | while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) |
| 169 | continue; |
| 170 | |
| 171 | /* |
| 172 | * For MOUThpm = 1000 MHz (MOUTapll) |
| 173 | * doutcopy = MOUThpm / (ratio + 1) = 200 (4) |
| 174 | * sclkhpm = doutcopy / (ratio + 1) = 200 (4) |
Przemyslaw Marczak | 239b171 | 2014-09-23 12:46:43 +0200 | [diff] [blame] | 175 | * cores_out = armclk / (ratio + 1) = 200 (4) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 176 | */ |
| 177 | clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); |
Przemyslaw Marczak | 239b171 | 2014-09-23 12:46:43 +0200 | [diff] [blame] | 178 | set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4); |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 179 | |
| 180 | clrsetbits_le32(&clk->div_cpu1, clr, set); |
| 181 | |
| 182 | /* Wait for divider ready status */ |
| 183 | while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING) |
| 184 | continue; |
| 185 | |
| 186 | /* |
| 187 | * Set CMU_DMC clocks src to APLL |
| 188 | * Bit values: 0 ; 1 |
| 189 | * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL |
| 190 | * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL |
| 191 | * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL |
| 192 | * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT |
| 193 | * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI) |
| 194 | * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL |
| 195 | * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL |
| 196 | * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1 |
| 197 | */ |
| 198 | clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | |
| 199 | MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) | |
| 200 | MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) | |
| 201 | MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); |
| 202 | set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) | |
| 203 | MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) | |
| 204 | MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); |
| 205 | |
| 206 | clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); |
| 207 | |
| 208 | /* Wait for mux change */ |
| 209 | while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) |
| 210 | continue; |
| 211 | |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 212 | /* Set MPLL to 800MHz */ |
| 213 | set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 214 | |
| 215 | clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); |
| 216 | |
| 217 | /* Wait for PLL to be locked */ |
| 218 | while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) |
| 219 | continue; |
| 220 | |
| 221 | /* Switch back CMU_DMC mux */ |
| 222 | set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) | |
| 223 | MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) | |
| 224 | MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0); |
| 225 | |
| 226 | clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); |
| 227 | |
| 228 | /* Wait for mux change */ |
| 229 | while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) |
| 230 | continue; |
| 231 | |
| 232 | /* CLK_DIV_DMC0 */ |
| 233 | clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | |
| 234 | DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7); |
| 235 | /* |
| 236 | * For: |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 237 | * MOUTdmc = 800 MHz |
| 238 | * MOUTdphy = 800 MHz |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 239 | * |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 240 | * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) |
| 241 | * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) |
| 242 | * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) |
| 243 | * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) |
| 244 | * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) |
| 245 | * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 246 | */ |
| 247 | set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | |
| 248 | DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); |
| 249 | |
| 250 | clrsetbits_le32(&clk->div_dmc0, clr, set); |
| 251 | |
| 252 | /* Wait for divider ready status */ |
| 253 | while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING) |
| 254 | continue; |
| 255 | |
| 256 | /* CLK_DIV_DMC1 */ |
| 257 | clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | |
| 258 | C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127); |
| 259 | /* |
| 260 | * For: |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 261 | * MOUTg2d = 800 MHz |
| 262 | * MOUTc2c = 800 Mhz |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 263 | * MOUTpwi = 108 MHz |
| 264 | * |
Joonyoung Shim | 400bed2 | 2015-01-23 17:30:07 +0900 | [diff] [blame] | 265 | * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 266 | * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) |
| 267 | * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 268 | * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) |
| 269 | */ |
Joonyoung Shim | 400bed2 | 2015-01-23 17:30:07 +0900 | [diff] [blame] | 270 | set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 271 | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); |
| 272 | |
| 273 | clrsetbits_le32(&clk->div_dmc1, clr, set); |
| 274 | |
| 275 | /* Wait for divider ready status */ |
| 276 | while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING) |
| 277 | continue; |
| 278 | |
| 279 | /* CLK_SRC_PERIL0 */ |
| 280 | clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | |
| 281 | UART3_SEL(15) | UART4_SEL(15); |
| 282 | /* |
| 283 | * Set CLK_SRC_PERIL0 clocks src to MPLL |
| 284 | * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0); |
| 285 | * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL); |
| 286 | * 8(SCLK_VPLL) |
| 287 | * |
| 288 | * Set all to SCLK_MPLL_USER_T |
| 289 | */ |
| 290 | set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) | |
| 291 | UART4_SEL(6); |
| 292 | |
| 293 | clrsetbits_le32(&clk->src_peril0, clr, set); |
| 294 | |
| 295 | /* CLK_DIV_PERIL0 */ |
| 296 | clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | |
| 297 | UART3_RATIO(15) | UART4_RATIO(15); |
| 298 | /* |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 299 | * For MOUTuart0-4: 800MHz |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 300 | * |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 301 | * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 302 | */ |
| 303 | set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | |
| 304 | UART3_RATIO(7) | UART4_RATIO(7); |
| 305 | |
| 306 | clrsetbits_le32(&clk->div_peril0, clr, set); |
| 307 | |
| 308 | while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING) |
| 309 | continue; |
| 310 | |
| 311 | /* CLK_DIV_FSYS1 */ |
| 312 | clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | |
| 313 | MMC1_PRE_RATIO(255); |
| 314 | /* |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 315 | * For MOUTmmc0-3 = 800 MHz (MPLL) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 316 | * |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 317 | * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) |
| 318 | * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) |
| 319 | * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) |
| 320 | * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 321 | */ |
| 322 | set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | |
| 323 | MMC1_PRE_RATIO(1); |
| 324 | |
| 325 | clrsetbits_le32(&clk->div_fsys1, clr, set); |
| 326 | |
| 327 | /* Wait for divider ready status */ |
| 328 | while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) |
| 329 | continue; |
| 330 | |
| 331 | /* CLK_DIV_FSYS2 */ |
| 332 | clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | |
| 333 | MMC3_PRE_RATIO(255); |
| 334 | /* |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 335 | * For MOUTmmc0-3 = 800 MHz (MPLL) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 336 | * |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 337 | * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) |
| 338 | * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) |
| 339 | * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) |
| 340 | * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 341 | */ |
| 342 | set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | |
| 343 | MMC3_PRE_RATIO(1); |
| 344 | |
| 345 | clrsetbits_le32(&clk->div_fsys2, clr, set); |
| 346 | |
| 347 | /* Wait for divider ready status */ |
| 348 | while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING) |
| 349 | continue; |
| 350 | |
| 351 | /* CLK_DIV_FSYS3 */ |
| 352 | clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); |
| 353 | /* |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 354 | * For MOUTmmc4 = 800 MHz (MPLL) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 355 | * |
Minkyu Kang | ec54c59 | 2014-09-11 14:02:03 +0900 | [diff] [blame] | 356 | * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) |
| 357 | * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 358 | */ |
| 359 | set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0); |
| 360 | |
| 361 | clrsetbits_le32(&clk->div_fsys3, clr, set); |
| 362 | |
| 363 | /* Wait for divider ready status */ |
| 364 | while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING) |
| 365 | continue; |
| 366 | |
| 367 | return; |
| 368 | } |
| 369 | |
| 370 | static void board_gpio_init(void) |
| 371 | { |
| 372 | /* eMMC Reset Pin */ |
Przemyslaw Marczak | 4157375 | 2014-10-28 17:31:07 +0100 | [diff] [blame] | 373 | gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset"); |
| 374 | |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 375 | gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); |
| 376 | gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); |
| 377 | gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X); |
| 378 | |
| 379 | /* Enable FAN (Odroid U3) */ |
Przemyslaw Marczak | 4157375 | 2014-10-28 17:31:07 +0100 | [diff] [blame] | 380 | gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control"); |
| 381 | |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 382 | gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); |
| 383 | gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); |
| 384 | gpio_direction_output(EXYNOS4X12_GPIO_D00, 1); |
| 385 | |
| 386 | /* OTG Vbus output (Odroid U3+) */ |
Przemyslaw Marczak | 4157375 | 2014-10-28 17:31:07 +0100 | [diff] [blame] | 387 | gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus"); |
| 388 | |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 389 | gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); |
| 390 | gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); |
| 391 | gpio_direction_output(EXYNOS4X12_GPIO_L20, 0); |
| 392 | |
| 393 | /* OTG INT (Odroid U3+) */ |
Przemyslaw Marczak | 4157375 | 2014-10-28 17:31:07 +0100 | [diff] [blame] | 394 | gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT"); |
| 395 | |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 396 | gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); |
| 397 | gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); |
| 398 | gpio_direction_input(EXYNOS4X12_GPIO_X31); |
Suriyan Ramasami | 4de08b5 | 2014-11-20 17:26:30 -0800 | [diff] [blame] | 399 | |
Suriyan Ramasami | a29cfb1 | 2014-11-23 22:15:32 -0800 | [diff] [blame] | 400 | /* Blue LED (Odroid X2/U2/U3) */ |
| 401 | gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED"); |
| 402 | |
| 403 | gpio_direction_output(EXYNOS4X12_GPIO_C10, 0); |
| 404 | |
Suriyan Ramasami | 4de08b5 | 2014-11-20 17:26:30 -0800 | [diff] [blame] | 405 | #ifdef CONFIG_CMD_USB |
| 406 | /* USB3503A Reference frequency */ |
| 407 | gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq"); |
| 408 | |
| 409 | /* USB3503A Connect */ |
| 410 | gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect"); |
| 411 | |
| 412 | /* USB3503A Reset */ |
| 413 | gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset"); |
| 414 | #endif |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 415 | } |
| 416 | |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 417 | int exynos_early_init_f(void) |
| 418 | { |
| 419 | board_clock_init(); |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 420 | |
| 421 | return 0; |
| 422 | } |
| 423 | |
| 424 | int exynos_init(void) |
| 425 | { |
Przemyslaw Marczak | 4157375 | 2014-10-28 17:31:07 +0100 | [diff] [blame] | 426 | board_gpio_init(); |
| 427 | |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 428 | return 0; |
| 429 | } |
| 430 | |
| 431 | int exynos_power_init(void) |
| 432 | { |
Minkyu Kang | abf4a62 | 2015-10-23 16:15:04 +0900 | [diff] [blame] | 433 | const char *mmc_regulators[] = { |
| 434 | "VDDQ_EMMC_1.8V", |
| 435 | "VDDQ_EMMC_2.8V", |
| 436 | "TFLASH_2.8V", |
| 437 | NULL, |
| 438 | }; |
| 439 | |
Przemyslaw Marczak | 75692a3 | 2015-05-13 13:38:27 +0200 | [diff] [blame] | 440 | if (regulator_list_autoset(mmc_regulators, NULL, true)) |
Seung-Woo Kim | ca21166 | 2018-06-04 16:03:05 +0900 | [diff] [blame] | 441 | pr_err("Unable to init all mmc regulators\n"); |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 442 | |
| 443 | return 0; |
| 444 | } |
| 445 | |
| 446 | #ifdef CONFIG_USB_GADGET |
| 447 | static int s5pc210_phy_control(int on) |
| 448 | { |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 449 | struct udevice *dev; |
| 450 | int ret; |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 451 | |
Przemyslaw Marczak | 75692a3 | 2015-05-13 13:38:27 +0200 | [diff] [blame] | 452 | ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev); |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 453 | if (ret) { |
Seung-Woo Kim | ca21166 | 2018-06-04 16:03:05 +0900 | [diff] [blame] | 454 | pr_err("Regulator get error: %d\n", ret); |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 455 | return ret; |
| 456 | } |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 457 | |
| 458 | if (on) |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 459 | return regulator_set_mode(dev, OPMODE_ON); |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 460 | else |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 461 | return regulator_set_mode(dev, OPMODE_LPM); |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 462 | } |
| 463 | |
Marek Vasut | 6939aca | 2015-12-04 02:23:29 +0100 | [diff] [blame] | 464 | struct dwc2_plat_otg_data s5pc210_otg_data = { |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 465 | .phy_control = s5pc210_phy_control, |
| 466 | .regs_phy = EXYNOS4X12_USBPHY_BASE, |
| 467 | .regs_otg = EXYNOS4X12_USBOTG_BASE, |
| 468 | .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL, |
| 469 | .usb_flags = PHY0_SLEEP, |
| 470 | }; |
Suriyan Ramasami | 97f4ef6 | 2014-10-29 09:22:43 -0700 | [diff] [blame] | 471 | #endif |
| 472 | |
| 473 | #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB) |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 474 | |
Krzysztof Kozlowski | 1b2b382 | 2019-03-06 10:23:09 +0100 | [diff] [blame] | 475 | static void set_usb3503_ref_clk(void) |
| 476 | { |
| 477 | #ifdef CONFIG_BOARD_TYPES |
| 478 | /* |
| 479 | * gpx3-0 chooses primary (low) or secondary (high) reference clock |
| 480 | * frequencies table. The choice of clock is done through hard-wired |
| 481 | * REF_SEL pins. |
| 482 | * The Odroid Us have reference clock at 24 MHz (00 entry from secondary |
| 483 | * table) and Odroid Xs have it at 26 MHz (01 entry from primary table). |
| 484 | */ |
| 485 | if (gd->board_type == ODROID_TYPE_U3) |
| 486 | gpio_direction_output(EXYNOS4X12_GPIO_X30, 0); |
| 487 | else |
| 488 | gpio_direction_output(EXYNOS4X12_GPIO_X30, 1); |
| 489 | #else |
| 490 | /* Choose Odroid Xs frequency without board types */ |
| 491 | gpio_direction_output(EXYNOS4X12_GPIO_X30, 1); |
| 492 | #endif /* CONFIG_BOARD_TYPES */ |
| 493 | } |
| 494 | |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 495 | int board_usb_init(int index, enum usb_init_type init) |
| 496 | { |
Suriyan Ramasami | 97f4ef6 | 2014-10-29 09:22:43 -0700 | [diff] [blame] | 497 | #ifdef CONFIG_CMD_USB |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 498 | struct udevice *dev; |
| 499 | int ret; |
Suriyan Ramasami | 97f4ef6 | 2014-10-29 09:22:43 -0700 | [diff] [blame] | 500 | |
Krzysztof Kozlowski | 1b2b382 | 2019-03-06 10:23:09 +0100 | [diff] [blame] | 501 | set_usb3503_ref_clk(); |
Suriyan Ramasami | 97f4ef6 | 2014-10-29 09:22:43 -0700 | [diff] [blame] | 502 | |
| 503 | /* Disconnect, Reset, Connect */ |
| 504 | gpio_direction_output(EXYNOS4X12_GPIO_X34, 0); |
| 505 | gpio_direction_output(EXYNOS4X12_GPIO_X35, 0); |
| 506 | gpio_direction_output(EXYNOS4X12_GPIO_X35, 1); |
| 507 | gpio_direction_output(EXYNOS4X12_GPIO_X34, 1); |
| 508 | |
| 509 | /* Power off and on BUCK8 for LAN9730 */ |
| 510 | debug("LAN9730 - Turning power buck 8 OFF and ON.\n"); |
| 511 | |
Przemyslaw Marczak | 75692a3 | 2015-05-13 13:38:27 +0200 | [diff] [blame] | 512 | ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev); |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 513 | if (ret) { |
Seung-Woo Kim | ca21166 | 2018-06-04 16:03:05 +0900 | [diff] [blame] | 514 | pr_err("Regulator get error: %d\n", ret); |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 515 | return ret; |
Suriyan Ramasami | 97f4ef6 | 2014-10-29 09:22:43 -0700 | [diff] [blame] | 516 | } |
| 517 | |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 518 | ret = regulator_set_enable(dev, true); |
| 519 | if (ret) { |
Seung-Woo Kim | ca21166 | 2018-06-04 16:03:05 +0900 | [diff] [blame] | 520 | pr_err("Regulator %s enable setting error: %d\n", dev->name, ret); |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 521 | return ret; |
| 522 | } |
Suriyan Ramasami | 97f4ef6 | 2014-10-29 09:22:43 -0700 | [diff] [blame] | 523 | |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 524 | ret = regulator_set_value(dev, 750000); |
| 525 | if (ret) { |
Seung-Woo Kim | ca21166 | 2018-06-04 16:03:05 +0900 | [diff] [blame] | 526 | pr_err("Regulator %s value setting error: %d\n", dev->name, ret); |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 527 | return ret; |
| 528 | } |
| 529 | |
| 530 | ret = regulator_set_value(dev, 3300000); |
| 531 | if (ret) { |
Seung-Woo Kim | ca21166 | 2018-06-04 16:03:05 +0900 | [diff] [blame] | 532 | pr_err("Regulator %s value setting error: %d\n", dev->name, ret); |
Przemyslaw Marczak | e7781bc | 2015-05-13 13:38:25 +0200 | [diff] [blame] | 533 | return ret; |
| 534 | } |
| 535 | #endif |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 536 | debug("USB_udc_probe\n"); |
Marek Vasut | 01b61fa | 2015-12-04 02:26:33 +0100 | [diff] [blame] | 537 | return dwc2_udc_probe(&s5pc210_otg_data); |
Przemyslaw Marczak | 0b217aa | 2014-09-01 13:50:51 +0200 | [diff] [blame] | 538 | } |
| 539 | #endif |