| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Linus Walleij | d222d1b | 2012-01-30 13:49:34 +0000 | [diff] [blame] | 2 | /* |
| 3 | * arch/arm/include/asm/hardware/pci_v3.h |
| 4 | * |
| 5 | * Internal header file PCI V3 chip |
| 6 | * |
| 7 | * Copyright (C) ARM Limited |
| 8 | * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. |
| Linus Walleij | d222d1b | 2012-01-30 13:49:34 +0000 | [diff] [blame] | 9 | */ |
| 10 | #ifndef ASM_ARM_HARDWARE_PCI_V3_H |
| 11 | #define ASM_ARM_HARDWARE_PCI_V3_H |
| 12 | |
| 13 | /* ------------------------------------------------------------------------------- |
| 14 | * V3 Local Bus to PCI Bridge definitions |
| 15 | * ------------------------------------------------------------------------------- |
| 16 | * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 |
| 17 | * All V3 register names are prefaced by V3_ to avoid clashing with any other |
| 18 | * PCI definitions. Their names match the user's manual. |
| 19 | * |
| 20 | * I'm assuming that I20 is disabled. |
| 21 | * |
| 22 | */ |
| 23 | #define V3_PCI_VENDOR 0x00000000 |
| 24 | #define V3_PCI_DEVICE 0x00000002 |
| 25 | #define V3_PCI_CMD 0x00000004 |
| 26 | #define V3_PCI_STAT 0x00000006 |
| 27 | #define V3_PCI_CC_REV 0x00000008 |
| 28 | #define V3_PCI_HDR_CFG 0x0000000C |
| 29 | #define V3_PCI_IO_BASE 0x00000010 |
| 30 | #define V3_PCI_BASE0 0x00000014 |
| 31 | #define V3_PCI_BASE1 0x00000018 |
| 32 | #define V3_PCI_SUB_VENDOR 0x0000002C |
| 33 | #define V3_PCI_SUB_ID 0x0000002E |
| 34 | #define V3_PCI_ROM 0x00000030 |
| 35 | #define V3_PCI_BPARAM 0x0000003C |
| 36 | #define V3_PCI_MAP0 0x00000040 |
| 37 | #define V3_PCI_MAP1 0x00000044 |
| 38 | #define V3_PCI_INT_STAT 0x00000048 |
| 39 | #define V3_PCI_INT_CFG 0x0000004C |
| 40 | #define V3_LB_BASE0 0x00000054 |
| 41 | #define V3_LB_BASE1 0x00000058 |
| 42 | #define V3_LB_MAP0 0x0000005E |
| 43 | #define V3_LB_MAP1 0x00000062 |
| 44 | #define V3_LB_BASE2 0x00000064 |
| 45 | #define V3_LB_MAP2 0x00000066 |
| 46 | #define V3_LB_SIZE 0x00000068 |
| 47 | #define V3_LB_IO_BASE 0x0000006E |
| 48 | #define V3_FIFO_CFG 0x00000070 |
| 49 | #define V3_FIFO_PRIORITY 0x00000072 |
| 50 | #define V3_FIFO_STAT 0x00000074 |
| 51 | #define V3_LB_ISTAT 0x00000076 |
| 52 | #define V3_LB_IMASK 0x00000077 |
| 53 | #define V3_SYSTEM 0x00000078 |
| 54 | #define V3_LB_CFG 0x0000007A |
| 55 | #define V3_PCI_CFG 0x0000007C |
| 56 | #define V3_DMA_PCI_ADR0 0x00000080 |
| 57 | #define V3_DMA_PCI_ADR1 0x00000090 |
| 58 | #define V3_DMA_LOCAL_ADR0 0x00000084 |
| 59 | #define V3_DMA_LOCAL_ADR1 0x00000094 |
| 60 | #define V3_DMA_LENGTH0 0x00000088 |
| 61 | #define V3_DMA_LENGTH1 0x00000098 |
| 62 | #define V3_DMA_CSR0 0x0000008B |
| 63 | #define V3_DMA_CSR1 0x0000009B |
| 64 | #define V3_DMA_CTLB_ADR0 0x0000008C |
| 65 | #define V3_DMA_CTLB_ADR1 0x0000009C |
| 66 | #define V3_DMA_DELAY 0x000000E0 |
| 67 | #define V3_MAIL_DATA 0x000000C0 |
| 68 | #define V3_PCI_MAIL_IEWR 0x000000D0 |
| 69 | #define V3_PCI_MAIL_IERD 0x000000D2 |
| 70 | #define V3_LB_MAIL_IEWR 0x000000D4 |
| 71 | #define V3_LB_MAIL_IERD 0x000000D6 |
| 72 | #define V3_MAIL_WR_STAT 0x000000D8 |
| 73 | #define V3_MAIL_RD_STAT 0x000000DA |
| 74 | #define V3_QBA_MAP 0x000000DC |
| 75 | |
| 76 | /* PCI COMMAND REGISTER bits |
| 77 | */ |
| 78 | #define V3_COMMAND_M_FBB_EN (1 << 9) |
| 79 | #define V3_COMMAND_M_SERR_EN (1 << 8) |
| 80 | #define V3_COMMAND_M_PAR_EN (1 << 6) |
| 81 | #define V3_COMMAND_M_MASTER_EN (1 << 2) |
| 82 | #define V3_COMMAND_M_MEM_EN (1 << 1) |
| 83 | #define V3_COMMAND_M_IO_EN (1 << 0) |
| 84 | |
| 85 | /* SYSTEM REGISTER bits |
| 86 | */ |
| 87 | #define V3_SYSTEM_M_RST_OUT (1 << 15) |
| 88 | #define V3_SYSTEM_M_LOCK (1 << 14) |
| 89 | |
| 90 | /* PCI_CFG bits |
| 91 | */ |
| 92 | #define V3_PCI_CFG_M_I2O_EN (1 << 15) |
| 93 | #define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) |
| 94 | #define V3_PCI_CFG_M_IO_DIS (1 << 13) |
| 95 | #define V3_PCI_CFG_M_EN3V (1 << 12) |
| 96 | #define V3_PCI_CFG_M_RETRY_EN (1 << 10) |
| 97 | #define V3_PCI_CFG_M_AD_LOW1 (1 << 9) |
| 98 | #define V3_PCI_CFG_M_AD_LOW0 (1 << 8) |
| 99 | |
| 100 | /* PCI_BASE register bits (PCI -> Local Bus) |
| 101 | */ |
| 102 | #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 |
| 103 | #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 |
| 104 | #define V3_PCI_BASE_M_PREFETCH (1 << 3) |
| 105 | #define V3_PCI_BASE_M_TYPE (3 << 1) |
| 106 | #define V3_PCI_BASE_M_IO (1 << 0) |
| 107 | |
| 108 | /* PCI MAP register bits (PCI -> Local bus) |
| 109 | */ |
| 110 | #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 |
| 111 | #define V3_PCI_MAP_M_RD_POST_INH (1 << 15) |
| 112 | #define V3_PCI_MAP_M_ROM_SIZE (3 << 10) |
| 113 | #define V3_PCI_MAP_M_SWAP (3 << 8) |
| 114 | #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 |
| 115 | #define V3_PCI_MAP_M_REG_EN (1 << 1) |
| 116 | #define V3_PCI_MAP_M_ENABLE (1 << 0) |
| 117 | |
| 118 | #define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4) |
| 119 | #define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4) |
| 120 | #define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4) |
| 121 | #define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4) |
| 122 | #define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4) |
| 123 | #define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4) |
| 124 | #define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4) |
| 125 | #define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4) |
| 126 | #define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4) |
| 127 | #define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4) |
| 128 | #define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4) |
| 129 | #define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4) |
| 130 | |
| 131 | /* |
| 132 | * LB_BASE0,1 register bits (Local bus -> PCI) |
| 133 | */ |
| 134 | #define V3_LB_BASE_ADR_BASE 0xfff00000 |
| 135 | #define V3_LB_BASE_SWAP (3 << 8) |
| 136 | #define V3_LB_BASE_ADR_SIZE (15 << 4) |
| 137 | #define V3_LB_BASE_PREFETCH (1 << 3) |
| 138 | #define V3_LB_BASE_ENABLE (1 << 0) |
| 139 | |
| 140 | #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) |
| 141 | #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) |
| 142 | #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) |
| 143 | #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) |
| 144 | #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) |
| 145 | #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) |
| 146 | #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) |
| 147 | #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) |
| 148 | #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) |
| 149 | #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) |
| 150 | #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) |
| 151 | #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) |
| 152 | |
| 153 | #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) |
| 154 | |
| 155 | /* |
| 156 | * LB_MAP0,1 register bits (Local bus -> PCI) |
| 157 | */ |
| 158 | #define V3_LB_MAP_MAP_ADR 0xfff0 |
| 159 | #define V3_LB_MAP_TYPE (7 << 1) |
| 160 | #define V3_LB_MAP_AD_LOW_EN (1 << 0) |
| 161 | |
| 162 | #define V3_LB_MAP_TYPE_IACK (0 << 1) |
| 163 | #define V3_LB_MAP_TYPE_IO (1 << 1) |
| 164 | #define V3_LB_MAP_TYPE_MEM (3 << 1) |
| 165 | #define V3_LB_MAP_TYPE_CONFIG (5 << 1) |
| 166 | #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) |
| 167 | |
| 168 | /* PCI MAP register bits (PCI -> Local bus) */ |
| 169 | #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) |
| 170 | |
| 171 | /* |
| 172 | * LB_BASE2 register bits (Local bus -> PCI IO) |
| 173 | */ |
| 174 | #define V3_LB_BASE2_ADR_BASE 0xff00 |
| 175 | #define V3_LB_BASE2_SWAP (3 << 6) |
| 176 | #define V3_LB_BASE2_ENABLE (1 << 0) |
| 177 | |
| 178 | #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) |
| 179 | |
| 180 | /* |
| 181 | * LB_MAP2 register bits (Local bus -> PCI IO) |
| 182 | */ |
| 183 | #define V3_LB_MAP2_MAP_ADR 0xff00 |
| 184 | |
| 185 | #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) |
| 186 | |
| 187 | #endif |