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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +000011 */
12
13/*
14 * CPU specific code
15 */
16
17#include <common.h>
18#include <command.h>
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020019#include <asm/system.h>
Albert ARIBAUD21505f92014-04-15 16:13:48 +020020#include <asm/io.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000021
Wolfgang Denk6405a152006-03-31 18:32:53 +020022#ifdef CONFIG_USE_IRQ
23DECLARE_GLOBAL_DATA_PTR;
24#endif
25
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020026static void cache_flush(void);
27
wdenk4a9cbbe2002-08-27 09:48:53 +000028int cleanup_before_linux (void)
29{
30 /*
31 * this function is called just before we call linux
32 * it prepares the processor for linux
33 *
34 * just disable everything that can disturb booting linux
35 */
36
wdenk4a9cbbe2002-08-27 09:48:53 +000037 disable_interrupts ();
38
39 /* turn off I-cache */
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020040 icache_disable();
41 dcache_disable();
wdenk4a9cbbe2002-08-27 09:48:53 +000042
43 /* flush I-cache */
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020044 cache_flush();
wdenk4a9cbbe2002-08-27 09:48:53 +000045
46 return (0);
47}
48
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020049/* flush I/D-cache */
50static void cache_flush (void)
wdenk4a9cbbe2002-08-27 09:48:53 +000051{
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020052 unsigned long i = 0;
wdenk4a9cbbe2002-08-27 09:48:53 +000053
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020054 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
wdenk4a9cbbe2002-08-27 09:48:53 +000055}
Albert ARIBAUD21505f92014-04-15 16:13:48 +020056
57#define RST_BASE 0x90030000
58#define RSRR 0x00
59#define RCSR 0x04
60
61__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
62{
63 /* repeat endlessly */
64 while (1) {
65 writel(0, RST_BASE + RCSR);
66 writel(1, RST_BASE + RSRR);
67 }
68}