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wdenkbb1b8262003-03-27 12:09:35 +00001/*
wdenk8d5d28a2005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenkbb1b8262003-03-27 12:09:35 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This file contains the configuration parameters for the INCA-IP board.
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
32#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
33
Daniel Schwierzeckc56514c2011-07-27 13:22:36 +020034#define CONFIG_XWAY_SWAP_BYTES
35
Shinya Kuribayashi9b844372011-02-05 18:33:36 +090036/*
37 * Clock for the MIPS core (MHz)
38 * allowed values: 100000000, 133000000, and 150000000 (default)
39 */
40#ifndef CONFIG_CPU_CLOCK_RATE
41#define CONFIG_CPU_CLOCK_RATE 150000000
wdenk5d841732003-08-17 18:55:18 +000042#endif
wdenkbb1b8262003-03-27 12:09:35 +000043
Daniel Schwierzeck6ff8ae02011-07-27 13:22:37 +020044#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */
wdenkbb1b8262003-03-27 12:09:35 +000045
wdenkb02744a2003-04-05 00:53:31 +000046#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkbb1b8262003-03-27 12:09:35 +000047
wdenkb02744a2003-04-05 00:53:31 +000048#define CONFIG_BAUDRATE 115200
wdenkbb1b8262003-03-27 12:09:35 +000049
wdenkb02744a2003-04-05 00:53:31 +000050#define CONFIG_TIMESTAMP /* Print image info with timestamp */
51
52#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +010053 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkb02744a2003-04-05 00:53:31 +000054 "echo"
55
56#undef CONFIG_BOOTARGS
57
58#define CONFIG_EXTRA_ENV_SETTINGS \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010060 "nfsroot=${serverip}:${rootpath}\0" \
wdenkb02744a2003-04-05 00:53:31 +000061 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010062 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off\0" \
65 "addmisc=setenv bootargs ${bootargs} " \
66 "console=ttyS0,${baudrate} " \
67 "ethaddr=${ethaddr} " \
wdenkb02744a2003-04-05 00:53:31 +000068 "panic=1\0" \
69 "flash_nfs=run nfsargs addip addmisc;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010070 "bootm ${kernel_addr}\0" \
wdenkb02744a2003-04-05 00:53:31 +000071 "flash_self=run ramargs addip addmisc;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010072 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
73 "net_nfs=tftp 80500000 ${bootfile};" \
wdenkb02744a2003-04-05 00:53:31 +000074 "run nfsargs addip addmisc;bootm\0" \
75 "rootpath=/opt/eldk/mips_4KC\0" \
76 "bootfile=/tftpboot/INCA/uImage\0" \
77 "kernel_addr=B0040000\0" \
78 "ramdisk_addr=B0100000\0" \
79 "u-boot=/tftpboot/INCA/u-boot.bin\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010080 "load=tftp 80500000 ${u-boot}\0" \
wdenkb02744a2003-04-05 00:53:31 +000081 "update=protect off 1:0-2;era 1:0-2;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010082 "cp.b 80500000 B0000000 ${filesize}\0" \
wdenkb02744a2003-04-05 00:53:31 +000083 ""
84#define CONFIG_BOOTCOMMAND "run flash_self"
85
Jon Loeliger860435b2007-07-04 22:32:32 -050086
87/*
Jon Loeliger140b69c2007-07-10 09:38:02 -050088 * BOOTP options
89 */
90#define CONFIG_BOOTP_BOOTFILESIZE
91#define CONFIG_BOOTP_BOOTPATH
92#define CONFIG_BOOTP_GATEWAY
93#define CONFIG_BOOTP_HOSTNAME
94
95
96/*
Jon Loeliger860435b2007-07-04 22:32:32 -050097 * Command line configuration.
98 */
99#include <config_cmd_default.h>
100
101#define CONFIG_CMD_ASKENV
102#define CONFIG_CMD_DHCP
103#define CONFIG_CMD_ELF
104#define CONFIG_CMD_JFFS2
105#define CONFIG_CMD_NFS
106#define CONFIG_CMD_PING
107#define CONFIG_CMD_SNTP
108
wdenkbb1b8262003-03-27 12:09:35 +0000109
110/*
111 * Miscellaneous configurable options
112 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200113#define CONFIG_SYS_LONGHELP /* undef to save memory */
114#define CONFIG_SYS_PROMPT "INCA-IP # " /* Monitor Command Prompt */
115#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
116#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
117#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
wdenkbb1b8262003-03-27 12:09:35 +0000118
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_MALLOC_LEN 128*1024
wdenkb02744a2003-04-05 00:53:31 +0000120
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
wdenkb02744a2003-04-05 00:53:31 +0000122
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_MIPS_TIMER_FREQ (incaip_get_cpuclk() / 2)
Shinya Kuribayashi5d374e02008-06-05 22:29:00 +0900124
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#define CONFIG_SYS_HZ 1000
wdenkb02744a2003-04-05 00:53:31 +0000126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_SDRAM_BASE 0x80000000
wdenkb02744a2003-04-05 00:53:31 +0000128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_LOAD_ADDR 0x80100000 /* default load address */
wdenkbb1b8262003-03-27 12:09:35 +0000130
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_MEMTEST_START 0x80100000
132#define CONFIG_SYS_MEMTEST_END 0x80800000
wdenkbb1b8262003-03-27 12:09:35 +0000133
134/*-----------------------------------------------------------------------
135 * FLASH and environment organization
136 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
138#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenkbb1b8262003-03-27 12:09:35 +0000139
140#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */
141#define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */
142
143/* The following #defines are needed to get flash environment right */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200144#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_MONITOR_LEN (192 << 10)
wdenkbb1b8262003-03-27 12:09:35 +0000146
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
wdenkbb1b8262003-03-27 12:09:35 +0000148
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkbb1b8262003-03-27 12:09:35 +0000150
151/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
153#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkbb1b8262003-03-27 12:09:35 +0000154
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200155#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbb1b8262003-03-27 12:09:35 +0000156
157/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200158#define CONFIG_ENV_ADDR 0xB0030000
159#define CONFIG_ENV_SIZE 0x10000
wdenkbb1b8262003-03-27 12:09:35 +0000160
161#define CONFIG_FLASH_16BIT
162
163#define CONFIG_NR_DRAM_BANKS 1
164
165#define CONFIG_INCA_IP_SWITCH
wdenkdb82c8e2004-02-26 23:01:04 +0000166#define CONFIG_INCA_IP_SWITCH_AMDIX
wdenkbb1b8262003-03-27 12:09:35 +0000167
Wolfgang Denk47f57792005-08-08 01:03:24 +0200168/*
169 * JFFS2 partitions
170 */
171/* No command line, one static partition, use all space on the device */
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100172#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk47f57792005-08-08 01:03:24 +0200173#define CONFIG_JFFS2_DEV "nor1"
174#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
175#define CONFIG_JFFS2_PART_OFFSET 0x00000000
176
177/* mtdparts command line support */
178/*
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100179#define CONFIG_CMD_MTDPARTS
Wolfgang Denk47f57792005-08-08 01:03:24 +0200180#define MTDIDS_DEFAULT "nor0=INCA-IP Bank 0"
181#define MTDPARTS_DEFAULT "mtdparts=INCA-IP Bank 0:192k(uboot)," \
182 "64k(env)," \
183 "768k(linux)," \
184 "1m@3m(rootfs)," \
185 "768k(linux2)," \
186 "3m@5m(rootfs2)"
187*/
wdenkdf28aa02003-12-12 00:02:26 +0000188
wdenkbb1b8262003-03-27 12:09:35 +0000189/*-----------------------------------------------------------------------
190 * Cache Configuration
191 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#define CONFIG_SYS_DCACHE_SIZE 4096
193#define CONFIG_SYS_ICACHE_SIZE 4096
194#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkbb1b8262003-03-27 12:09:35 +0000195
196#endif /* __CONFIG_H */