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Kumar Galae1c09492010-07-15 16:49:03 -05001/*
ramneek mehresh3d339632012-04-18 19:39:53 +00002 * Copyright 2009-2012 Freescale Semiconductor, Inc.
Kumar Galae1c09492010-07-15 16:49:03 -05003 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Galae1c09492010-07-15 16:49:03 -05005 */
6
7/*
8 * Corenet DS style board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
York Sun4bd582d2014-04-30 14:43:49 -070013#define CONFIG_DISPLAY_BOARDINFO
14
Kumar Galae1c09492010-07-15 16:49:03 -050015#include "../board/freescale/common/ics307_clk.h"
16
Shaohui Xie25a2b392011-03-16 10:10:32 +080017#ifdef CONFIG_RAMBOOT_PBL
Aneesh Bansale0f50152015-06-16 10:36:00 +053018#ifdef CONFIG_SECURE_BOOT
Shaohui Xie25a2b392011-03-16 10:10:32 +080019#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Aneesh Bansale0f50152015-06-16 10:36:00 +053021#ifdef CONFIG_NAND
22#define CONFIG_RAMBOOT_NAND
23#endif
Aneesh Bansalb69061d2015-06-16 10:36:43 +053024#define CONFIG_BOOTSCRIPT_COPY_RAM
Aneesh Bansale0f50152015-06-16 10:36:00 +053025#else
26#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090028#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
Shaohui Xieea65fd82012-08-10 02:49:35 +000029#if defined(CONFIG_P3041DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090030#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
Shaohui Xieea65fd82012-08-10 02:49:35 +000031#elif defined(CONFIG_P4080DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090032#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
Shaohui Xieea65fd82012-08-10 02:49:35 +000033#elif defined(CONFIG_P5020DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090034#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
Shaohui Xie171d0d22013-03-25 07:40:11 +000035#elif defined(CONFIG_P5040DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090036#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
Shaohui Xieea65fd82012-08-10 02:49:35 +000037#endif
Shaohui Xie25a2b392011-03-16 10:10:32 +080038#endif
Aneesh Bansale0f50152015-06-16 10:36:00 +053039#endif
Shaohui Xie25a2b392011-03-16 10:10:32 +080040
Liu Gangb4611ee2012-08-09 05:10:03 +000041#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
Liu Gang1e084582012-03-08 00:33:18 +000042/* Set 1M boot space */
Liu Gangb4611ee2012-08-09 05:10:03 +000043#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
44#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
45 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
Liu Gang1e084582012-03-08 00:33:18 +000046#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
47#define CONFIG_SYS_NO_FLASH
48#endif
49
Kumar Galae1c09492010-07-15 16:49:03 -050050/* High Level Configuration Options */
51#define CONFIG_BOOKE
52#define CONFIG_E500 /* BOOKE e500 family */
53#define CONFIG_E500MC /* BOOKE e500mc family */
54#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Kumar Galae1c09492010-07-15 16:49:03 -050055#define CONFIG_MP /* support multiple processors */
56
Kumar Gala51832132010-10-20 16:02:41 -050057#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053058#define CONFIG_SYS_TEXT_BASE 0xeff40000
Kumar Gala51832132010-10-20 16:02:41 -050059#endif
60
Kumar Galae727a362011-01-12 02:48:53 -060061#ifndef CONFIG_RESET_VECTOR_ADDRESS
62#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
63#endif
64
Kumar Galae1c09492010-07-15 16:49:03 -050065#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
66#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
67#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
Ruchika Gupta12af67f2014-10-15 11:35:31 +053068#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Kumar Galae1c09492010-07-15 16:49:03 -050069#define CONFIG_PCI /* Enable PCI/PCIE */
Robert P. J. Daya8099812016-05-03 19:52:49 -040070#define CONFIG_PCIE1 /* PCIE controller 1 */
71#define CONFIG_PCIE2 /* PCIE controller 2 */
Kumar Galae1c09492010-07-15 16:49:03 -050072#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
73#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
Kumar Galae1c09492010-07-15 16:49:03 -050074
Kumar Galae1c09492010-07-15 16:49:03 -050075#define CONFIG_FSL_LAW /* Use common FSL init code */
76
77#define CONFIG_ENV_OVERWRITE
78
79#ifdef CONFIG_SYS_NO_FLASH
Liu Gangb4611ee2012-08-09 05:10:03 +000080#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
Kumar Galae1c09492010-07-15 16:49:03 -050081#define CONFIG_ENV_IS_NOWHERE
Liu Gang85bcd732012-03-08 00:33:20 +000082#endif
Kumar Galae1c09492010-07-15 16:49:03 -050083#else
Kumar Galae1c09492010-07-15 16:49:03 -050084#define CONFIG_FLASH_CFI_DRIVER
85#define CONFIG_SYS_FLASH_CFI
York Sun7b1559d2011-06-30 11:00:56 -070086#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Shaohui Xiec6083892011-05-12 18:46:40 +080087#endif
88
89#if defined(CONFIG_SPIFLASH)
90#define CONFIG_SYS_EXTRA_ENV_RELOC
91#define CONFIG_ENV_IS_IN_SPI_FLASH
92#define CONFIG_ENV_SPI_BUS 0
93#define CONFIG_ENV_SPI_CS 0
94#define CONFIG_ENV_SPI_MAX_HZ 10000000
95#define CONFIG_ENV_SPI_MODE 0
96#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
97#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
98#define CONFIG_ENV_SECT_SIZE 0x10000
99#elif defined(CONFIG_SDCARD)
100#define CONFIG_SYS_EXTRA_ENV_RELOC
101#define CONFIG_ENV_IS_IN_MMC
Fabio Estevamae8c45e2012-01-11 09:20:50 +0000102#define CONFIG_FSL_FIXED_MMC_LOCATION
Shaohui Xiec6083892011-05-12 18:46:40 +0800103#define CONFIG_SYS_MMC_ENV_DEV 0
104#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +0530105#define CONFIG_ENV_OFFSET (512 * 1658)
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800106#elif defined(CONFIG_NAND)
107#define CONFIG_SYS_EXTRA_ENV_RELOC
108#define CONFIG_ENV_IS_IN_NAND
109#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +0530110#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gangb4611ee2012-08-09 05:10:03 +0000111#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gang85bcd732012-03-08 00:33:20 +0000112#define CONFIG_ENV_IS_IN_REMOTE
113#define CONFIG_ENV_ADDR 0xffe20000
114#define CONFIG_ENV_SIZE 0x2000
Liu Gang170fae22012-03-08 00:33:15 +0000115#elif defined(CONFIG_ENV_IS_NOWHERE)
116#define CONFIG_ENV_SIZE 0x2000
Shaohui Xiec6083892011-05-12 18:46:40 +0800117#else
118#define CONFIG_ENV_IS_IN_FLASH
Shaohui Xie25a2b392011-03-16 10:10:32 +0800119#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Shaohui Xiec6083892011-05-12 18:46:40 +0800120#define CONFIG_ENV_SIZE 0x2000
121#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Kumar Galae1c09492010-07-15 16:49:03 -0500122#endif
123
124#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
Kumar Galae1c09492010-07-15 16:49:03 -0500125
126/*
127 * These can be toggled for performance analysis, otherwise use default.
128 */
129#define CONFIG_SYS_CACHE_STASHING
130#define CONFIG_BACKSIDE_L2_CACHE
131#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
132#define CONFIG_BTB /* toggle branch predition */
York Sun147fde12011-01-10 12:02:58 +0000133#define CONFIG_DDR_ECC
Kumar Galae1c09492010-07-15 16:49:03 -0500134#ifdef CONFIG_DDR_ECC
135#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
136#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
137#endif
138
139#define CONFIG_ENABLE_36BIT_PHYS
140
141#ifdef CONFIG_PHYS_64BIT
142#define CONFIG_ADDR_MAP
143#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
144#endif
145
York Sun18acc8b2010-09-28 15:20:36 -0700146#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
Kumar Galae1c09492010-07-15 16:49:03 -0500147#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
148#define CONFIG_SYS_MEMTEST_END 0x00400000
149#define CONFIG_SYS_ALT_MEMTEST
150#define CONFIG_PANIC_HANG /* do not reset board on panic */
151
152/*
Shaohui Xie25a2b392011-03-16 10:10:32 +0800153 * Config the L3 Cache as L3 SRAM
154 */
155#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
156#ifdef CONFIG_PHYS_64BIT
157#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
158#else
159#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
160#endif
161#define CONFIG_SYS_L3_SIZE (1024 << 10)
162#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
163
Kumar Galae1c09492010-07-15 16:49:03 -0500164#ifdef CONFIG_PHYS_64BIT
165#define CONFIG_SYS_DCSRBAR 0xf0000000
166#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
167#endif
168
169/* EEPROM */
170#define CONFIG_ID_EEPROM
171#define CONFIG_SYS_I2C_EEPROM_NXID
172#define CONFIG_SYS_EEPROM_BUS_NUM 0
173#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
174#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
175
176/*
177 * DDR Setup
178 */
179#define CONFIG_VERY_BIG_RAM
180#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
181#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
182
183#define CONFIG_DIMM_SLOTS_PER_CTLR 1
york0b2bb6d2010-07-02 22:25:59 +0000184#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
Kumar Galae1c09492010-07-15 16:49:03 -0500185
186#define CONFIG_DDR_SPD
York Sunf0626592013-09-30 09:22:09 -0700187#define CONFIG_SYS_FSL_DDR3
Kumar Galae1c09492010-07-15 16:49:03 -0500188
Kumar Galae1c09492010-07-15 16:49:03 -0500189#define CONFIG_SYS_SPD_BUS_NUM 1
190#define SPD_EEPROM_ADDRESS1 0x51
191#define SPD_EEPROM_ADDRESS2 0x52
Kumar Galae38209e2011-02-09 02:00:08 +0000192#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
York Sun269c7eb2010-10-18 13:46:49 -0700193#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
Kumar Galae1c09492010-07-15 16:49:03 -0500194
195/*
196 * Local Bus Definitions
197 */
198
199/* Set the local bus clock 1/8 of platform clock */
200#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
201
202#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
203#ifdef CONFIG_PHYS_64BIT
204#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
205#else
206#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
207#endif
208
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800209#define CONFIG_SYS_FLASH_BR_PRELIM \
Timur Tabib56570c2012-07-06 07:39:26 +0000210 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800211 | BR_PS_16 | BR_V)
212#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
Kumar Galae1c09492010-07-15 16:49:03 -0500213 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
214
215#define CONFIG_SYS_BR1_PRELIM \
216 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
217#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
218
Kumar Galae1c09492010-07-15 16:49:03 -0500219#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
220#ifdef CONFIG_PHYS_64BIT
221#define PIXIS_BASE_PHYS 0xfffdf0000ull
222#else
223#define PIXIS_BASE_PHYS PIXIS_BASE
224#endif
225
226#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
227#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
228
229#define PIXIS_LBMAP_SWITCH 7
230#define PIXIS_LBMAP_MASK 0xf0
231#define PIXIS_LBMAP_SHIFT 4
232#define PIXIS_LBMAP_ALTBANK 0x40
233
234#define CONFIG_SYS_FLASH_QUIET_TEST
235#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
236
237#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
238#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
239#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
240#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
241
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200242#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kumar Galae1c09492010-07-15 16:49:03 -0500243
Shaohui Xie25a2b392011-03-16 10:10:32 +0800244#if defined(CONFIG_RAMBOOT_PBL)
245#define CONFIG_SYS_RAMBOOT
246#endif
247
Kumar Galae38209e2011-02-09 02:00:08 +0000248/* Nand Flash */
Kumar Galae38209e2011-02-09 02:00:08 +0000249#ifdef CONFIG_NAND_FSL_ELBC
250#define CONFIG_SYS_NAND_BASE 0xffa00000
251#ifdef CONFIG_PHYS_64BIT
252#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
253#else
254#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
255#endif
256
257#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
258#define CONFIG_SYS_MAX_NAND_DEVICE 1
Kumar Galae38209e2011-02-09 02:00:08 +0000259#define CONFIG_CMD_NAND
260#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
261
262/* NAND flash config */
263#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
264 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
265 | BR_PS_8 /* Port Size = 8 bit */ \
266 | BR_MS_FCM /* MSEL = FCM */ \
267 | BR_V) /* valid */
268#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
269 | OR_FCM_PGS /* Large Page*/ \
270 | OR_FCM_CSCT \
271 | OR_FCM_CST \
272 | OR_FCM_CHT \
273 | OR_FCM_SCY_1 \
274 | OR_FCM_TRLX \
275 | OR_FCM_EHTR)
276
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800277#ifdef CONFIG_NAND
278#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
279#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
280#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
281#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
282#else
283#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
284#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
285#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
286#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
287#endif
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800288#else
289#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
290#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
Kumar Galad0af3b92011-08-31 09:50:13 -0500291#endif /* CONFIG_NAND_FSL_ELBC */
Kumar Galae38209e2011-02-09 02:00:08 +0000292
Kumar Galae1c09492010-07-15 16:49:03 -0500293#define CONFIG_SYS_FLASH_EMPTY_INFO
294#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
295#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
296
297#define CONFIG_BOARD_EARLY_INIT_F
298#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
299#define CONFIG_MISC_INIT_R
300
301#define CONFIG_HWCONFIG
302
303/* define to use L1 as initial stack */
304#define CONFIG_L1_INIT_RAM
305#define CONFIG_SYS_INIT_RAM_LOCK
306#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
307#ifdef CONFIG_PHYS_64BIT
308#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
309#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
310/* The assembler doesn't like typecast */
311#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
312 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
313 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
314#else
315#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
316#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
317#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
318#endif
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200319#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Galae1c09492010-07-15 16:49:03 -0500320
Wolfgang Denk0191e472010-10-26 14:34:52 +0200321#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kumar Galae1c09492010-07-15 16:49:03 -0500322#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
323
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530324#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Kumar Galae1c09492010-07-15 16:49:03 -0500325#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
326
327/* Serial Port - controlled on board with jumper J8
328 * open - index 2
329 * shorted - index 1
330 */
331#define CONFIG_CONS_INDEX 1
Kumar Galae1c09492010-07-15 16:49:03 -0500332#define CONFIG_SYS_NS16550_SERIAL
333#define CONFIG_SYS_NS16550_REG_SIZE 1
334#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
335
336#define CONFIG_SYS_BAUDRATE_TABLE \
337 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
338
339#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
340#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
341#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
342#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
343
Kumar Galae1c09492010-07-15 16:49:03 -0500344/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200345#define CONFIG_SYS_I2C
346#define CONFIG_SYS_I2C_FSL
347#define CONFIG_SYS_FSL_I2C_SPEED 400000
348#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
349#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
350#define CONFIG_SYS_FSL_I2C2_SPEED 400000
351#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
352#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
Kumar Galae1c09492010-07-15 16:49:03 -0500353
354/*
355 * RapidIO
356 */
Kumar Gala8975d7a2010-12-30 12:09:53 -0600357#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500358#ifdef CONFIG_PHYS_64BIT
Kumar Gala8975d7a2010-12-30 12:09:53 -0600359#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500360#else
Kumar Gala8975d7a2010-12-30 12:09:53 -0600361#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500362#endif
Kumar Gala8975d7a2010-12-30 12:09:53 -0600363#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
Kumar Galae1c09492010-07-15 16:49:03 -0500364
Kumar Gala8975d7a2010-12-30 12:09:53 -0600365#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500366#ifdef CONFIG_PHYS_64BIT
Kumar Gala8975d7a2010-12-30 12:09:53 -0600367#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500368#else
Kumar Gala8975d7a2010-12-30 12:09:53 -0600369#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500370#endif
Kumar Gala8975d7a2010-12-30 12:09:53 -0600371#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
Kumar Galae1c09492010-07-15 16:49:03 -0500372
373/*
Liu Gang4cc85322012-03-08 00:33:17 +0000374 * for slave u-boot IMAGE instored in master memory space,
375 * PHYS must be aligned based on the SIZE
376 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800377#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
378#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
379#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
380#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Liu Gang85bcd732012-03-08 00:33:20 +0000381/*
Liu Gangd7b17a92012-08-09 05:09:59 +0000382 * for slave UCODE and ENV instored in master memory space,
Liu Gang85bcd732012-03-08 00:33:20 +0000383 * PHYS must be aligned based on the SIZE
384 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800385#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Liu Gang99e0c292012-08-09 05:10:02 +0000386#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
387#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
Liu Gangd7b17a92012-08-09 05:09:59 +0000388
Liu Gangf420aa92012-03-08 00:33:21 +0000389/* slave core release by master*/
Liu Gang99e0c292012-08-09 05:10:02 +0000390#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
391#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
Liu Gang4cc85322012-03-08 00:33:17 +0000392
393/*
Liu Gangb4611ee2012-08-09 05:10:03 +0000394 * SRIO_PCIE_BOOT - SLAVE
Liu Gang1e084582012-03-08 00:33:18 +0000395 */
Liu Gangb4611ee2012-08-09 05:10:03 +0000396#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
397#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
398#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
399 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
Liu Gang1e084582012-03-08 00:33:18 +0000400#endif
401
402/*
Shaohui Xie58649792011-05-12 18:46:14 +0800403 * eSPI - Enhanced SPI
404 */
Shaohui Xie58649792011-05-12 18:46:14 +0800405#define CONFIG_SF_DEFAULT_SPEED 10000000
406#define CONFIG_SF_DEFAULT_MODE 0
407
408/*
Kumar Galae1c09492010-07-15 16:49:03 -0500409 * General PCI
410 * Memory space is mapped 1-1, but I/O space must start from 0.
411 */
412
413/* controller 1, direct to uli, tgtid 3, Base address 20000 */
414#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
415#ifdef CONFIG_PHYS_64BIT
416#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
417#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
418#else
419#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
420#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
421#endif
422#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
423#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
424#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
425#ifdef CONFIG_PHYS_64BIT
426#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
427#else
428#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
429#endif
430#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
431
432/* controller 2, Slot 2, tgtid 2, Base address 201000 */
433#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
434#ifdef CONFIG_PHYS_64BIT
435#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
436#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
437#else
438#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
439#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
440#endif
441#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
442#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
443#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
444#ifdef CONFIG_PHYS_64BIT
445#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
446#else
447#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
448#endif
449#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
450
451/* controller 3, Slot 1, tgtid 1, Base address 202000 */
Trübenbach, Ralfd8ec2c02011-04-20 13:04:47 +0000452#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500453#ifdef CONFIG_PHYS_64BIT
454#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
455#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
456#else
457#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
458#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
459#endif
460#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
461#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
462#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
463#ifdef CONFIG_PHYS_64BIT
464#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
465#else
466#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
467#endif
468#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
469
Kumar Gala67a6dfe2010-07-09 09:12:18 -0500470/* controller 4, Base address 203000 */
471#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
472#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
473#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
474#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
475#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
476#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
477
Kumar Galae1c09492010-07-15 16:49:03 -0500478/* Qman/Bman */
Haiying Wang325a12f2011-01-20 22:26:31 +0000479#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Kumar Galae1c09492010-07-15 16:49:03 -0500480#define CONFIG_SYS_BMAN_NUM_PORTALS 10
481#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
482#ifdef CONFIG_PHYS_64BIT
483#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
484#else
485#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
486#endif
487#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500488#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
489#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
490#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
491#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
492#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
493 CONFIG_SYS_BMAN_CENA_SIZE)
494#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
495#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Kumar Galae1c09492010-07-15 16:49:03 -0500496#define CONFIG_SYS_QMAN_NUM_PORTALS 10
497#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
498#ifdef CONFIG_PHYS_64BIT
499#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
500#else
501#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
502#endif
503#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500504#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
505#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
506#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
507#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
508#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
509 CONFIG_SYS_QMAN_CENA_SIZE)
510#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
511#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Kumar Galae1c09492010-07-15 16:49:03 -0500512
513#define CONFIG_SYS_DPAA_FMAN
514#define CONFIG_SYS_DPAA_PME
515/* Default address of microcode for the Linux Fman driver */
Timur Tabibb763662011-05-03 13:35:11 -0500516#if defined(CONFIG_SPIFLASH)
517/*
518 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
519 * env, so we got 0x110000.
520 */
Timur Tabi275f4bb2011-11-22 09:21:25 -0600521#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiang83a90842014-03-21 16:21:44 +0800522#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Timur Tabibb763662011-05-03 13:35:11 -0500523#elif defined(CONFIG_SDCARD)
524/*
525 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +0530526 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
527 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Timur Tabibb763662011-05-03 13:35:11 -0500528 */
Timur Tabi275f4bb2011-11-22 09:21:25 -0600529#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiang83a90842014-03-21 16:21:44 +0800530#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
Timur Tabibb763662011-05-03 13:35:11 -0500531#elif defined(CONFIG_NAND)
Timur Tabi275f4bb2011-11-22 09:21:25 -0600532#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Zhao Qiang83a90842014-03-21 16:21:44 +0800533#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gangb4611ee2012-08-09 05:10:03 +0000534#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gang1e084582012-03-08 00:33:18 +0000535/*
536 * Slave has no ucode locally, it can fetch this from remote. When implementing
537 * in two corenet boards, slave's ucode could be stored in master's memory
538 * space, the address can be mapped from slave TLB->slave LAW->
Liu Gangb4611ee2012-08-09 05:10:03 +0000539 * slave SRIO or PCIE outbound window->master inbound window->
540 * master LAW->the ucode address in master's memory space.
Liu Gang1e084582012-03-08 00:33:18 +0000541 */
542#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiang83a90842014-03-21 16:21:44 +0800543#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Kumar Galae1c09492010-07-15 16:49:03 -0500544#else
Timur Tabi275f4bb2011-11-22 09:21:25 -0600545#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiang83a90842014-03-21 16:21:44 +0800546#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Kumar Galae1c09492010-07-15 16:49:03 -0500547#endif
Timur Tabi275f4bb2011-11-22 09:21:25 -0600548#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
549#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
Kumar Galae1c09492010-07-15 16:49:03 -0500550
551#ifdef CONFIG_SYS_DPAA_FMAN
552#define CONFIG_FMAN_ENET
Andy Fleming79ce05b2010-10-20 15:35:16 -0500553#define CONFIG_PHYLIB_10G
554#define CONFIG_PHY_VITESSE
555#define CONFIG_PHY_TERANETICS
Kumar Galae1c09492010-07-15 16:49:03 -0500556#endif
557
558#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000559#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Galae1c09492010-07-15 16:49:03 -0500560#define CONFIG_PCI_PNP /* do pci plug-and-play */
Kumar Galae1c09492010-07-15 16:49:03 -0500561
Kumar Galae1c09492010-07-15 16:49:03 -0500562#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
563#define CONFIG_DOS_PARTITION
564#endif /* CONFIG_PCI */
565
566/* SATA */
567#ifdef CONFIG_FSL_SATA_V2
568#define CONFIG_LIBATA
569#define CONFIG_FSL_SATA
570
571#define CONFIG_SYS_SATA_MAX_DEVICE 2
572#define CONFIG_SATA1
573#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
574#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
575#define CONFIG_SATA2
576#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
577#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
578
579#define CONFIG_LBA48
580#define CONFIG_CMD_SATA
581#define CONFIG_DOS_PARTITION
Kumar Galae1c09492010-07-15 16:49:03 -0500582#endif
583
584#ifdef CONFIG_FMAN_ENET
585#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
586#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
587#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
588#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
589#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
590
Kumar Galae1c09492010-07-15 16:49:03 -0500591#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
592#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
593#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
594#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
595#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
Kumar Galae1c09492010-07-15 16:49:03 -0500596
597#define CONFIG_SYS_TBIPA_VALUE 8
598#define CONFIG_MII /* MII PHY management */
599#define CONFIG_ETHPRIME "FM1@DTSEC1"
600#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
601#endif
602
603/*
604 * Environment
605 */
Kumar Galae1c09492010-07-15 16:49:03 -0500606#define CONFIG_LOADS_ECHO /* echo on for serial download */
607#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
608
609/*
610 * Command line configuration.
611 */
Kumar Galae1c09492010-07-15 16:49:03 -0500612#define CONFIG_CMD_ERRATA
613#define CONFIG_CMD_IRQ
Kumar Galaaff60ff2011-08-31 09:16:02 -0500614#define CONFIG_CMD_REGINFO
Kumar Galae1c09492010-07-15 16:49:03 -0500615
616#ifdef CONFIG_PCI
617#define CONFIG_CMD_PCI
Kumar Galae1c09492010-07-15 16:49:03 -0500618#endif
619
620/*
621* USB
622*/
ramneek mehresh3d339632012-04-18 19:39:53 +0000623#define CONFIG_HAS_FSL_DR_USB
624#define CONFIG_HAS_FSL_MPH_USB
625
626#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
Kumar Galae1c09492010-07-15 16:49:03 -0500627#define CONFIG_USB_EHCI
628#define CONFIG_USB_EHCI_FSL
629#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
ramneek mehresh3d339632012-04-18 19:39:53 +0000630#endif
Kumar Galae1c09492010-07-15 16:49:03 -0500631
Kumar Galae1c09492010-07-15 16:49:03 -0500632#ifdef CONFIG_MMC
633#define CONFIG_FSL_ESDHC
634#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
635#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Kumar Galae1c09492010-07-15 16:49:03 -0500636#define CONFIG_GENERIC_MMC
Kumar Galae1c09492010-07-15 16:49:03 -0500637#define CONFIG_DOS_PARTITION
638#endif
639
Ruchika Gupta12af67f2014-10-15 11:35:31 +0530640/* Hash command with SHA acceleration supported in hardware */
641#ifdef CONFIG_FSL_CAAM
642#define CONFIG_CMD_HASH
643#define CONFIG_SHA_HW_ACCEL
644#endif
645
Kumar Galae1c09492010-07-15 16:49:03 -0500646/*
647 * Miscellaneous configurable options
648 */
649#define CONFIG_SYS_LONGHELP /* undef to save memory */
650#define CONFIG_CMDLINE_EDITING /* Command-line editing */
651#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
652#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Galae1c09492010-07-15 16:49:03 -0500653#ifdef CONFIG_CMD_KGDB
654#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
655#else
656#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
657#endif
658#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
659#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
660#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Kumar Galae1c09492010-07-15 16:49:03 -0500661
662/*
663 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500664 * have to be in the first 64 MB of memory, since this is
Kumar Galae1c09492010-07-15 16:49:03 -0500665 * the maximum mapped by the Linux kernel during initialization.
666 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500667#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
668#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Galae1c09492010-07-15 16:49:03 -0500669
Kumar Galae1c09492010-07-15 16:49:03 -0500670#ifdef CONFIG_CMD_KGDB
671#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Galae1c09492010-07-15 16:49:03 -0500672#endif
673
674/*
675 * Environment Configuration
676 */
Joe Hershberger257ff782011-10-13 13:03:47 +0000677#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000678#define CONFIG_BOOTFILE "uImage"
Kumar Galae1c09492010-07-15 16:49:03 -0500679#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
680
681/* default location for tftp and bootm */
682#define CONFIG_LOADADDR 1000000
683
Kumar Galae1c09492010-07-15 16:49:03 -0500684
685#define CONFIG_BAUDRATE 115200
686
Timur Tabif7886b72012-08-14 06:47:27 +0000687#ifdef CONFIG_P4080DS
Ramneek Mehresha0cce272011-06-07 10:10:43 +0000688#define __USB_PHY_TYPE ulpi
689#else
690#define __USB_PHY_TYPE utmi
691#endif
692
Kumar Galae1c09492010-07-15 16:49:03 -0500693#define CONFIG_EXTRA_ENV_SETTINGS \
Emil Medveb250d372010-08-31 22:57:43 -0500694 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
Ramneek Mehresha0cce272011-06-07 10:10:43 +0000695 "bank_intlv=cs0_cs1;" \
ramneek mehresh1b57b002013-09-10 17:37:45 +0530696 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
697 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
Kumar Galae1c09492010-07-15 16:49:03 -0500698 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200699 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
700 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Emil Medveb250d372010-08-31 22:57:43 -0500701 "tftpflash=tftpboot $loadaddr $uboot && " \
702 "protect off $ubootaddr +$filesize && " \
703 "erase $ubootaddr +$filesize && " \
704 "cp.b $loadaddr $ubootaddr $filesize && " \
705 "protect on $ubootaddr +$filesize && " \
706 "cmp.b $loadaddr $ubootaddr $filesize\0" \
Kumar Galae1c09492010-07-15 16:49:03 -0500707 "consoledev=ttyS0\0" \
708 "ramdiskaddr=2000000\0" \
709 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500710 "fdtaddr=1e00000\0" \
Kumar Galae1c09492010-07-15 16:49:03 -0500711 "fdtfile=p4080ds/p4080ds.dtb\0" \
Kim Phillips1dedccc2014-05-14 19:33:45 -0500712 "bdev=sda3\0"
Kumar Galae1c09492010-07-15 16:49:03 -0500713
714#define CONFIG_HDBOOT \
715 "setenv bootargs root=/dev/$bdev rw " \
716 "console=$consoledev,$baudrate $othbootargs;" \
717 "tftp $loadaddr $bootfile;" \
718 "tftp $fdtaddr $fdtfile;" \
719 "bootm $loadaddr - $fdtaddr"
720
721#define CONFIG_NFSBOOTCOMMAND \
722 "setenv bootargs root=/dev/nfs rw " \
723 "nfsroot=$serverip:$rootpath " \
724 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
725 "console=$consoledev,$baudrate $othbootargs;" \
726 "tftp $loadaddr $bootfile;" \
727 "tftp $fdtaddr $fdtfile;" \
728 "bootm $loadaddr - $fdtaddr"
729
730#define CONFIG_RAMBOOTCOMMAND \
731 "setenv bootargs root=/dev/ram rw " \
732 "console=$consoledev,$baudrate $othbootargs;" \
733 "tftp $ramdiskaddr $ramdiskfile;" \
734 "tftp $loadaddr $bootfile;" \
735 "tftp $fdtaddr $fdtfile;" \
736 "bootm $loadaddr $ramdiskaddr $fdtaddr"
737
738#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
739
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000740#include <asm/fsl_secure_boot.h>
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000741
Kumar Galae1c09492010-07-15 16:49:03 -0500742#endif /* __CONFIG_H */