Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 0951b9af02b591bd6e7bcb7dbe4b6bb18ec2fc2b / . / arch / arm / dts / am335x-guardian-u-boot.dtsi
blob: 26c011dacd421d6f68e9196477c6742f8aeeb479 [file] [log] [blame]
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
4 * Copyright (C) 2018 Robert Bosch Power Tools GmbH
5 */
6
Dario Binacchi2180d802020-12-30 00:06:37 +0100[diff] [blame]7#include "am33xx-u-boot.dtsi"
8
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]9/ {
10 ocp {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]11 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]12 };
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]13};
14
15&l4_wkup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]16 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]17};
18
Dario Binacchi67e92c12020-12-30 00:16:27 +0100[diff] [blame]19&l4_per {
20
21 segment@300000 {
22
23 target-module@e000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-all;
Dario Binacchi67e92c12020-12-30 00:16:27 +0100[diff] [blame]25
26 lcdc: lcdc@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-all;
Dario Binacchi67e92c12020-12-30 00:16:27 +0100[diff] [blame]28 };
29 };
30 };
31};
32
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]33&mmc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]35};
36
37&mmc1_pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]39};
40
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]41&scm {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]43};
44
Gireesh Hiremath6b755fa2021-06-11 16:13:47 +0000[diff] [blame]45&spi0 {
46 lcd0: display@0 {
47 compatible = "himax,hx8238d";
48 pinctrl-names = "default";
49 pinctrl-0 = <&lcd0_pins>;
50 reg = <0>;
51 label = "lcd";
52 spi-max-frequency = <100000>;
53 };
54};
55
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]56&uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]58};
59
60&uart0_pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]62};
63
64&usb {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]66};
67
68&usb_ctrl_mod {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]70};
71
72&usb0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]74};
75
76&usb0_phy {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]78};
79
80&am33xx_pinmux {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-all;
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]82
83 lcd0_pins: pinmux_lcd0_pins {
84 pinctrl-single,pins = <
Gireesh Hiremath88c11b22022-05-04 11:02:56 +0000[diff] [blame]85 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7)
Sjoerd Simonsf93564c2019-02-25 15:33:00 +0000[diff] [blame]86 >;
87 };
88};