blob: 9de9634cd5177a604eb955d1c01dec3d4eb23c96 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00002
3#include <common.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -06004#include <env.h>
wdenkc6097192002-11-03 00:24:07 +00005#include <malloc.h>
6#include <net.h>
Ben Warren840f8a52008-08-31 10:45:44 -07007#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +00008#include <pci.h>
9
wdenkc6097192002-11-03 00:24:07 +000010#undef DEBUG_SROM
11#undef DEBUG_SROM2
12
13#undef UPDATE_SROM
14
Marek Vasut81d10f72020-04-19 03:09:26 +020015/* PCI Registers. */
16#define PCI_CFDA_PSM 0x43
wdenkc6097192002-11-03 00:24:07 +000017
18#define CFRV_RN 0x000000f0 /* Revision Number */
19
20#define WAKEUP 0x00 /* Power Saving Wakeup */
21#define SLEEP 0x80 /* Power Saving Sleep Mode */
22
Marek Vasut81d10f72020-04-19 03:09:26 +020023#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
wdenkc6097192002-11-03 00:24:07 +000024
Marek Vasut81d10f72020-04-19 03:09:26 +020025/* Ethernet chip registers. */
wdenkc6097192002-11-03 00:24:07 +000026#define DE4X5_BMR 0x000 /* Bus Mode Register */
27#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
28#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
29#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
30#define DE4X5_STS 0x028 /* Status Register */
31#define DE4X5_OMR 0x030 /* Operation Mode Register */
32#define DE4X5_SICR 0x068 /* SIA Connectivity Register */
33#define DE4X5_APROM 0x048 /* Ethernet Address PROM */
34
Marek Vasut81d10f72020-04-19 03:09:26 +020035/* Register bits. */
wdenkc6097192002-11-03 00:24:07 +000036#define BMR_SWR 0x00000001 /* Software Reset */
37#define STS_TS 0x00700000 /* Transmit Process State */
38#define STS_RS 0x000e0000 /* Receive Process State */
39#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
40#define OMR_SR 0x00000002 /* Start/Stop Receive */
41#define OMR_PS 0x00040000 /* Port Select */
42#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
43#define OMR_PM 0x00000080 /* Pass All Multicast */
44
Marek Vasut81d10f72020-04-19 03:09:26 +020045/* Descriptor bits. */
wdenkc6097192002-11-03 00:24:07 +000046#define R_OWN 0x80000000 /* Own Bit */
47#define RD_RER 0x02000000 /* Receive End Of Ring */
48#define RD_LS 0x00000100 /* Last Descriptor */
49#define RD_ES 0x00008000 /* Error Summary */
50#define TD_TER 0x02000000 /* Transmit End Of Ring */
51#define T_OWN 0x80000000 /* Own Bit */
52#define TD_LS 0x40000000 /* Last Segment */
53#define TD_FS 0x20000000 /* First Segment */
54#define TD_ES 0x00008000 /* Error Summary */
55#define TD_SET 0x08000000 /* Setup Packet */
56
57/* The EEPROM commands include the alway-set leading bit. */
58#define SROM_WRITE_CMD 5
59#define SROM_READ_CMD 6
60#define SROM_ERASE_CMD 7
61
Marek Vasut81d10f72020-04-19 03:09:26 +020062#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
wdenkc6097192002-11-03 00:24:07 +000063#define SROM_RD 0x00004000 /* Read from Boot ROM */
Marek Vasut81d10f72020-04-19 03:09:26 +020064#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
65#define EE_WRITE_0 0x4801
66#define EE_WRITE_1 0x4805
67#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
wdenkc6097192002-11-03 00:24:07 +000068#define SROM_SR 0x00000800 /* Select Serial ROM when set */
69
70#define DT_IN 0x00000004 /* Serial Data In */
71#define DT_CLK 0x00000002 /* Serial ROM Clock */
72#define DT_CS 0x00000001 /* Serial ROM Chip Select */
73
74#define POLL_DEMAND 1
75
Marek Vasut75244fb2020-04-19 03:36:46 +020076#if defined(CONFIG_E500)
77#define phys_to_bus(a) (a)
78#else
79#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
80#endif
81
Marek Vasut5e2ad052020-04-19 04:00:49 +020082#define NUM_RX_DESC PKTBUFSRX
83#define NUM_TX_DESC 1 /* Number of TX descriptors */
84#define RX_BUFF_SZ PKTSIZE_ALIGN
85
86#define TOUT_LOOP 1000000
87
88#define SETUP_FRAME_LEN 192
89
90struct de4x5_desc {
91 volatile s32 status;
92 u32 des1;
93 u32 buf;
94 u32 next;
95};
96
97/* RX and TX descriptor ring */
98static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
99static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
100static int rx_new; /* RX descriptor ring pointer */
101static int tx_new; /* TX descriptor ring pointer */
102
103static char rx_ring_size;
104static char tx_ring_size;
105
Marek Vasutf02b7012020-04-19 03:40:03 +0200106static u32 dc2114x_inl(struct eth_device *dev, u32 addr)
Marek Vasut75244fb2020-04-19 03:36:46 +0200107{
Marek Vasutf02b7012020-04-19 03:40:03 +0200108 return le32_to_cpu(*(volatile u32 *)(addr + dev->iobase));
Marek Vasut75244fb2020-04-19 03:36:46 +0200109}
110
Marek Vasutf02b7012020-04-19 03:40:03 +0200111static void dc2114x_outl(struct eth_device *dev, u32 command, u32 addr)
Marek Vasut75244fb2020-04-19 03:36:46 +0200112{
Marek Vasutf02b7012020-04-19 03:40:03 +0200113 *(volatile u32 *)(addr + dev->iobase) = cpu_to_le32(command);
Marek Vasut75244fb2020-04-19 03:36:46 +0200114}
115
116static void reset_de4x5(struct eth_device *dev)
117{
Marek Vasutf02b7012020-04-19 03:40:03 +0200118 u32 i;
Marek Vasut75244fb2020-04-19 03:36:46 +0200119
Marek Vasutf02b7012020-04-19 03:40:03 +0200120 i = dc2114x_inl(dev, DE4X5_BMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200121 mdelay(1);
Marek Vasutf02b7012020-04-19 03:40:03 +0200122 dc2114x_outl(dev, i | BMR_SWR, DE4X5_BMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200123 mdelay(1);
Marek Vasutf02b7012020-04-19 03:40:03 +0200124 dc2114x_outl(dev, i, DE4X5_BMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200125 mdelay(1);
126
127 for (i = 0; i < 5; i++) {
Marek Vasutf02b7012020-04-19 03:40:03 +0200128 dc2114x_inl(dev, DE4X5_BMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200129 mdelay(10);
130 }
131
132 mdelay(1);
wdenkc6097192002-11-03 00:24:07 +0000133}
134
Marek Vasut75244fb2020-04-19 03:36:46 +0200135static void start_de4x5(struct eth_device *dev)
136{
Marek Vasutf02b7012020-04-19 03:40:03 +0200137 u32 omr;
Marek Vasut75244fb2020-04-19 03:36:46 +0200138
Marek Vasutf02b7012020-04-19 03:40:03 +0200139 omr = dc2114x_inl(dev, DE4X5_OMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200140 omr |= OMR_ST | OMR_SR;
Marek Vasutf02b7012020-04-19 03:40:03 +0200141 dc2114x_outl(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */
wdenkc6097192002-11-03 00:24:07 +0000142}
143
Marek Vasut75244fb2020-04-19 03:36:46 +0200144static void stop_de4x5(struct eth_device *dev)
145{
Marek Vasutf02b7012020-04-19 03:40:03 +0200146 u32 omr;
Marek Vasut75244fb2020-04-19 03:36:46 +0200147
Marek Vasutf02b7012020-04-19 03:40:03 +0200148 omr = dc2114x_inl(dev, DE4X5_OMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200149 omr &= ~(OMR_ST | OMR_SR);
Marek Vasutf02b7012020-04-19 03:40:03 +0200150 dc2114x_outl(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */
wdenkc6097192002-11-03 00:24:07 +0000151}
152
Marek Vasut5e2ad052020-04-19 04:00:49 +0200153/* SROM Read and write routines. */
154static void sendto_srom(struct eth_device *dev, u_int command, u_long addr)
155{
156 dc2114x_outl(dev, command, addr);
157 udelay(1);
158}
wdenkc6097192002-11-03 00:24:07 +0000159
Marek Vasut5e2ad052020-04-19 04:00:49 +0200160static int getfrom_srom(struct eth_device *dev, u_long addr)
161{
162 u32 tmp = dc2114x_inl(dev, addr);
wdenkc6097192002-11-03 00:24:07 +0000163
Marek Vasut5e2ad052020-04-19 04:00:49 +0200164 udelay(1);
165 return tmp;
166}
wdenkc6097192002-11-03 00:24:07 +0000167
Marek Vasut5e2ad052020-04-19 04:00:49 +0200168/* Note: this routine returns extra data bits for size detection. */
169static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location,
170 int addr_len)
171{
172 int read_cmd = location | (SROM_READ_CMD << addr_len);
173 unsigned int retval = 0;
174 int i;
wdenkc6097192002-11-03 00:24:07 +0000175
Marek Vasut5e2ad052020-04-19 04:00:49 +0200176 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
177 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000178
Marek Vasut5e2ad052020-04-19 04:00:49 +0200179#ifdef DEBUG_SROM
180 printf(" EEPROM read at %d ", location);
wdenkc6097192002-11-03 00:24:07 +0000181#endif
wdenkc6097192002-11-03 00:24:07 +0000182
Marek Vasut5e2ad052020-04-19 04:00:49 +0200183 /* Shift the read command bits out. */
184 for (i = 4 + addr_len; i >= 0; i--) {
185 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
wdenkc6097192002-11-03 00:24:07 +0000186
Marek Vasut5e2ad052020-04-19 04:00:49 +0200187 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval,
188 ioaddr);
189 udelay(10);
190 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
191 ioaddr);
192 udelay(10);
193#ifdef DEBUG_SROM2
194 printf("%X", getfrom_srom(dev, ioaddr) & 15);
195#endif
196 retval = (retval << 1) |
197 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
198 }
wdenkc6097192002-11-03 00:24:07 +0000199
Marek Vasut5e2ad052020-04-19 04:00:49 +0200200 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000201
Marek Vasut5e2ad052020-04-19 04:00:49 +0200202#ifdef DEBUG_SROM2
203 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
204#endif
wdenkc6097192002-11-03 00:24:07 +0000205
Marek Vasut5e2ad052020-04-19 04:00:49 +0200206 for (i = 16; i > 0; i--) {
207 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
208 udelay(10);
209#ifdef DEBUG_SROM2
210 printf("%X", getfrom_srom(dev, ioaddr) & 15);
211#endif
212 retval = (retval << 1) |
213 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
214 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
215 udelay(10);
216 }
wdenkc6097192002-11-03 00:24:07 +0000217
Marek Vasut5e2ad052020-04-19 04:00:49 +0200218 /* Terminate the EEPROM access. */
219 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000220
Marek Vasut5e2ad052020-04-19 04:00:49 +0200221#ifdef DEBUG_SROM2
222 printf(" EEPROM value at %d is %5.5x.\n", location, retval);
223#endif
wdenkc6097192002-11-03 00:24:07 +0000224
Marek Vasut5e2ad052020-04-19 04:00:49 +0200225 return retval;
226}
wdenkc6097192002-11-03 00:24:07 +0000227
Marek Vasut5e2ad052020-04-19 04:00:49 +0200228/*
229 * This executes a generic EEPROM command, typically a write or write
230 * enable. It returns the data output from the EEPROM, and thus may
231 * also be used for reads.
232 */
233static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd,
234 int cmd_len)
235{
236 unsigned int retval = 0;
wdenkc6097192002-11-03 00:24:07 +0000237
Marek Vasut5e2ad052020-04-19 04:00:49 +0200238#ifdef DEBUG_SROM
239 printf(" EEPROM op 0x%x: ", cmd);
240#endif
wdenkc6097192002-11-03 00:24:07 +0000241
Marek Vasut5e2ad052020-04-19 04:00:49 +0200242 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000243
Marek Vasut5e2ad052020-04-19 04:00:49 +0200244 /* Shift the command bits out. */
245 do {
246 short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
wdenkc6097192002-11-03 00:24:07 +0000247
Marek Vasut5e2ad052020-04-19 04:00:49 +0200248 sendto_srom(dev, dataval, ioaddr);
249 udelay(10);
Marek Vasut268cc5b2020-04-19 03:09:47 +0200250
Marek Vasut5e2ad052020-04-19 04:00:49 +0200251#ifdef DEBUG_SROM2
252 printf("%X", getfrom_srom(dev, ioaddr) & 15);
253#endif
Nobuhiro Iwamatsud45fa742010-10-19 14:03:40 +0900254
Marek Vasut5e2ad052020-04-19 04:00:49 +0200255 sendto_srom(dev, dataval | DT_CLK, ioaddr);
256 udelay(10);
257 retval = (retval << 1) |
258 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
259 } while (--cmd_len >= 0);
wdenk0260cd62004-01-02 15:01:32 +0000260
Marek Vasut5e2ad052020-04-19 04:00:49 +0200261 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000262
Marek Vasut5e2ad052020-04-19 04:00:49 +0200263 /* Terminate the EEPROM access. */
264 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000265
Marek Vasut5e2ad052020-04-19 04:00:49 +0200266#ifdef DEBUG_SROM
267 printf(" EEPROM result is 0x%5.5x.\n", retval);
268#endif
wdenkc6097192002-11-03 00:24:07 +0000269
Marek Vasut5e2ad052020-04-19 04:00:49 +0200270 return retval;
271}
Marek Vasut331e4ec2020-04-18 01:56:51 +0200272
Marek Vasut5e2ad052020-04-19 04:00:49 +0200273static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
274{
275 int ee_addr_size;
wdenkc6097192002-11-03 00:24:07 +0000276
Marek Vasut5e2ad052020-04-19 04:00:49 +0200277 ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
wdenkc6097192002-11-03 00:24:07 +0000278
Marek Vasut5e2ad052020-04-19 04:00:49 +0200279 return do_eeprom_cmd(dev, ioaddr, 0xffff |
280 (((SROM_READ_CMD << ee_addr_size) | index) << 16),
281 3 + ee_addr_size + 16);
wdenkc6097192002-11-03 00:24:07 +0000282}
283
Marek Vasut5e2ad052020-04-19 04:00:49 +0200284#ifdef UPDATE_SROM
285static int write_srom(struct eth_device *dev, u_long ioaddr, int index,
286 int new_value)
wdenkc6097192002-11-03 00:24:07 +0000287{
Marek Vasut5e2ad052020-04-19 04:00:49 +0200288 unsigned short newval;
289 int ee_addr_size;
Marek Vasut268cc5b2020-04-19 03:09:47 +0200290 int i;
wdenkc6097192002-11-03 00:24:07 +0000291
Marek Vasut5e2ad052020-04-19 04:00:49 +0200292 ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
wdenkc6097192002-11-03 00:24:07 +0000293
Marek Vasut5e2ad052020-04-19 04:00:49 +0200294 udelay(10 * 1000); /* test-only */
wdenkc6097192002-11-03 00:24:07 +0000295
Marek Vasut5e2ad052020-04-19 04:00:49 +0200296#ifdef DEBUG_SROM
297 printf("ee_addr_size=%d.\n", ee_addr_size);
298 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
299#endif
wdenkc6097192002-11-03 00:24:07 +0000300
Marek Vasut5e2ad052020-04-19 04:00:49 +0200301 /* Enable programming modes. */
302 do_eeprom_cmd(dev, ioaddr, 0x4f << (ee_addr_size - 4),
303 3 + ee_addr_size);
wdenkc6097192002-11-03 00:24:07 +0000304
Marek Vasut5e2ad052020-04-19 04:00:49 +0200305 /* Do the actual write. */
306 do_eeprom_cmd(dev, ioaddr, new_value |
307 (((SROM_WRITE_CMD << ee_addr_size) | index) << 16),
308 3 + ee_addr_size + 16);
309
310 /* Poll for write finished. */
311 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
312 for (i = 0; i < 10000; i++) { /* Typical 2000 ticks */
313 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
314 break;
wdenkc6097192002-11-03 00:24:07 +0000315 }
316
Marek Vasut5e2ad052020-04-19 04:00:49 +0200317#ifdef DEBUG_SROM
318 printf(" Write finished after %d ticks.\n", i);
319#endif
320
321 /* Disable programming. */
322 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size - 4)),
323 3 + ee_addr_size);
324
325 /* And read the result. */
326 newval = do_eeprom_cmd(dev, ioaddr,
327 (((SROM_READ_CMD << ee_addr_size) | index) << 16)
328 | 0xffff, 3 + ee_addr_size + 16);
329#ifdef DEBUG_SROM
330 printf(" New value at offset %d is %4.4x.\n", index, newval);
331#endif
332
333 return 1;
334}
335
336static void update_srom(struct eth_device *dev, bd_t *bis)
337{
338 static unsigned short eeprom[0x40] = {
339 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
340 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
341 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
342 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
343 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
344 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
345 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
346 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
347 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
348 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
349 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
350 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
351 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
352 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
353 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
354 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
355 };
356 uchar enetaddr[6];
357 int i;
358
359 /* Ethernet Addr... */
360 if (!eth_env_get_enetaddr("ethaddr", enetaddr))
361 return;
362
363 eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
364 eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
365 eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
366
367 for (i = 0; i < 0x40; i++)
368 write_srom(dev, DE4X5_APROM, i, eeprom[i]);
369}
370#endif /* UPDATE_SROM */
371
372static void send_setup_frame(struct eth_device *dev, bd_t *bis)
373{
374 char setup_frame[SETUP_FRAME_LEN];
375 char *pa = &setup_frame[0];
376 int i;
377
378 memset(pa, 0xff, SETUP_FRAME_LEN);
379
380 for (i = 0; i < ETH_ALEN; i++) {
381 *(pa + (i & 1)) = dev->enetaddr[i];
382 if (i & 0x01)
383 pa += 4;
wdenkc6097192002-11-03 00:24:07 +0000384 }
385
Marek Vasut5e2ad052020-04-19 04:00:49 +0200386 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
387 if (i < TOUT_LOOP)
388 continue;
wdenkc6097192002-11-03 00:24:07 +0000389
Marek Vasut5e2ad052020-04-19 04:00:49 +0200390 printf("%s: tx error buffer not ready\n", dev->name);
391 return;
392 }
wdenkc6097192002-11-03 00:24:07 +0000393
Marek Vasut5e2ad052020-04-19 04:00:49 +0200394 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0]));
395 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
396 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
wdenkc6097192002-11-03 00:24:07 +0000397
Marek Vasut5e2ad052020-04-19 04:00:49 +0200398 dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
wdenkc6097192002-11-03 00:24:07 +0000399
Marek Vasut5e2ad052020-04-19 04:00:49 +0200400 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
401 if (i < TOUT_LOOP)
402 continue;
wdenkc6097192002-11-03 00:24:07 +0000403
Marek Vasut5e2ad052020-04-19 04:00:49 +0200404 printf("%s: tx buffer not ready\n", dev->name);
405 return;
406 }
wdenkc6097192002-11-03 00:24:07 +0000407
Marek Vasut5e2ad052020-04-19 04:00:49 +0200408 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
409 printf("TX error status2 = 0x%08X\n",
410 le32_to_cpu(tx_ring[tx_new].status));
411 }
412
413 tx_new = (tx_new + 1) % NUM_TX_DESC;
wdenkc6097192002-11-03 00:24:07 +0000414}
415
Joe Hershbergercfb0cee2012-05-21 14:45:22 +0000416static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
wdenkc6097192002-11-03 00:24:07 +0000417{
Marek Vasute3ffef32020-04-19 03:10:14 +0200418 int status = -1;
419 int i;
wdenkc6097192002-11-03 00:24:07 +0000420
421 if (length <= 0) {
422 printf("%s: bad packet size: %d\n", dev->name, length);
Marek Vasute3ffef32020-04-19 03:10:14 +0200423 goto done;
wdenkc6097192002-11-03 00:24:07 +0000424 }
425
Marek Vasute3ffef32020-04-19 03:10:14 +0200426 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
427 if (i < TOUT_LOOP)
428 continue;
429
430 printf("%s: tx error buffer not ready\n", dev->name);
431 goto done;
wdenkc6097192002-11-03 00:24:07 +0000432 }
433
Marek Vasute3ffef32020-04-19 03:10:14 +0200434 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
435 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
wdenkc6097192002-11-03 00:24:07 +0000436 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
437
Marek Vasutf02b7012020-04-19 03:40:03 +0200438 dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
wdenkc6097192002-11-03 00:24:07 +0000439
Marek Vasute3ffef32020-04-19 03:10:14 +0200440 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
441 if (i < TOUT_LOOP)
442 continue;
443
444 printf(".%s: tx buffer not ready\n", dev->name);
445 goto done;
wdenkc6097192002-11-03 00:24:07 +0000446 }
447
448 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
wdenk0260cd62004-01-02 15:01:32 +0000449 tx_ring[tx_new].status = 0x0;
Marek Vasute3ffef32020-04-19 03:10:14 +0200450 goto done;
wdenkc6097192002-11-03 00:24:07 +0000451 }
452
453 status = length;
454
Marek Vasute3ffef32020-04-19 03:10:14 +0200455done:
456 tx_new = (tx_new + 1) % NUM_TX_DESC;
wdenkc6097192002-11-03 00:24:07 +0000457 return status;
458}
459
Marek Vasutf30abb72020-04-19 03:10:25 +0200460static int dc21x4x_recv(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000461{
Marek Vasutf30abb72020-04-19 03:10:25 +0200462 int length = 0;
463 u32 status;
wdenkc6097192002-11-03 00:24:07 +0000464
Marek Vasutf30abb72020-04-19 03:10:25 +0200465 while (true) {
466 status = le32_to_cpu(rx_ring[rx_new].status);
wdenkc6097192002-11-03 00:24:07 +0000467
Marek Vasutf30abb72020-04-19 03:10:25 +0200468 if (status & R_OWN)
wdenkc6097192002-11-03 00:24:07 +0000469 break;
wdenkc6097192002-11-03 00:24:07 +0000470
471 if (status & RD_LS) {
Marek Vasutf30abb72020-04-19 03:10:25 +0200472 /* Valid frame status. */
wdenkc6097192002-11-03 00:24:07 +0000473 if (status & RD_ES) {
Marek Vasutf30abb72020-04-19 03:10:25 +0200474 /* There was an error. */
wdenkc6097192002-11-03 00:24:07 +0000475 printf("RX error status = 0x%08X\n", status);
476 } else {
Marek Vasutf30abb72020-04-19 03:10:25 +0200477 /* A valid frame received. */
478 length = (le32_to_cpu(rx_ring[rx_new].status)
479 >> 16);
wdenkc6097192002-11-03 00:24:07 +0000480
Marek Vasutf30abb72020-04-19 03:10:25 +0200481 /* Pass the packet up to the protocol layers */
482 net_process_received_packet
483 (net_rx_packets[rx_new], length - 4);
wdenkc6097192002-11-03 00:24:07 +0000484 }
485
Marek Vasutf30abb72020-04-19 03:10:25 +0200486 /*
487 * Change buffer ownership for this frame,
488 * back to the adapter.
wdenkc6097192002-11-03 00:24:07 +0000489 */
490 rx_ring[rx_new].status = cpu_to_le32(R_OWN);
491 }
492
Marek Vasutf30abb72020-04-19 03:10:25 +0200493 /* Update entry information. */
Marek Vasut81d10f72020-04-19 03:09:26 +0200494 rx_new = (rx_new + 1) % rx_ring_size;
wdenkc6097192002-11-03 00:24:07 +0000495 }
496
497 return length;
498}
499
Marek Vasut5e2ad052020-04-19 04:00:49 +0200500static int dc21x4x_init(struct eth_device *dev, bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000501{
Marek Vasut5e2ad052020-04-19 04:00:49 +0200502 int i;
Marek Vasut1f346782020-04-19 03:10:30 +0200503 int devbusfn = (int)dev->priv;
wdenkc6097192002-11-03 00:24:07 +0000504
Marek Vasut5e2ad052020-04-19 04:00:49 +0200505 /* Ensure we're not sleeping. */
506 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
wdenkc6097192002-11-03 00:24:07 +0000507
Marek Vasut5e2ad052020-04-19 04:00:49 +0200508 reset_de4x5(dev);
wdenkc6097192002-11-03 00:24:07 +0000509
Marek Vasut5e2ad052020-04-19 04:00:49 +0200510 if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) {
511 printf("Error: Cannot reset ethernet controller.\n");
512 return -1;
513 }
wdenkc6097192002-11-03 00:24:07 +0000514
Marek Vasut5e2ad052020-04-19 04:00:49 +0200515 dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
wdenkc6097192002-11-03 00:24:07 +0000516
Marek Vasut5e2ad052020-04-19 04:00:49 +0200517 for (i = 0; i < NUM_RX_DESC; i++) {
518 rx_ring[i].status = cpu_to_le32(R_OWN);
519 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
520 rx_ring[i].buf =
521 cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
522 rx_ring[i].next = 0;
wdenkc6097192002-11-03 00:24:07 +0000523 }
524
Marek Vasut5e2ad052020-04-19 04:00:49 +0200525 for (i = 0; i < NUM_TX_DESC; i++) {
526 tx_ring[i].status = 0;
527 tx_ring[i].des1 = 0;
528 tx_ring[i].buf = 0;
529 tx_ring[i].next = 0;
wdenkc6097192002-11-03 00:24:07 +0000530 }
531
Marek Vasut5e2ad052020-04-19 04:00:49 +0200532 rx_ring_size = NUM_RX_DESC;
533 tx_ring_size = NUM_TX_DESC;
wdenkc6097192002-11-03 00:24:07 +0000534
Marek Vasut5e2ad052020-04-19 04:00:49 +0200535 /* Write the end of list marker to the descriptor lists. */
536 rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
537 tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
wdenkc6097192002-11-03 00:24:07 +0000538
Marek Vasut5e2ad052020-04-19 04:00:49 +0200539 /* Tell the adapter where the TX/RX rings are located. */
540 dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
541 dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);
Marek Vasute13635a2020-04-19 03:10:50 +0200542
Marek Vasut5e2ad052020-04-19 04:00:49 +0200543 start_de4x5(dev);
wdenkc6097192002-11-03 00:24:07 +0000544
Marek Vasut5e2ad052020-04-19 04:00:49 +0200545 tx_new = 0;
546 rx_new = 0;
wdenk0260cd62004-01-02 15:01:32 +0000547
Marek Vasut5e2ad052020-04-19 04:00:49 +0200548 send_setup_frame(dev, bis);
wdenkc6097192002-11-03 00:24:07 +0000549
Marek Vasut5e2ad052020-04-19 04:00:49 +0200550 return 0;
wdenkc6097192002-11-03 00:24:07 +0000551}
552
Marek Vasut5e2ad052020-04-19 04:00:49 +0200553static void dc21x4x_halt(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000554{
Marek Vasut5e2ad052020-04-19 04:00:49 +0200555 int devbusfn = (int)dev->priv;
wdenkc6097192002-11-03 00:24:07 +0000556
Marek Vasut5e2ad052020-04-19 04:00:49 +0200557 stop_de4x5(dev);
558 dc2114x_outl(dev, 0, DE4X5_SICR);
559
560 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
wdenkc6097192002-11-03 00:24:07 +0000561}
562
Marek Vasut5e2ad052020-04-19 04:00:49 +0200563static void read_hw_addr(struct eth_device *dev, bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000564{
Marek Vasut5e2ad052020-04-19 04:00:49 +0200565 u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
566 int i, j = 0;
Marek Vasutb46c7a02020-04-19 03:11:06 +0200567
Marek Vasut5e2ad052020-04-19 04:00:49 +0200568 for (i = 0; i < (ETH_ALEN >> 1); i++) {
569 tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i);
570 *p = le16_to_cpu(tmp);
571 j += *p++;
wdenkc6097192002-11-03 00:24:07 +0000572 }
573
Marek Vasut5e2ad052020-04-19 04:00:49 +0200574 if (!j || j == 0x2fffd) {
575 memset(dev->enetaddr, 0, ETH_ALEN);
576 debug("Warning: can't read HW address from SROM.\n");
577#ifdef UPDATE_SROM
578 update_srom(dev, bis);
wdenkc6097192002-11-03 00:24:07 +0000579#endif
wdenkc6097192002-11-03 00:24:07 +0000580 }
wdenkc6097192002-11-03 00:24:07 +0000581}
582
Marek Vasut5e2ad052020-04-19 04:00:49 +0200583static struct pci_device_id supported[] = {
584 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
585 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
586 { }
587};
wdenkc6097192002-11-03 00:24:07 +0000588
Marek Vasut5e2ad052020-04-19 04:00:49 +0200589int dc21x4x_initialize(bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000590{
Marek Vasut5e2ad052020-04-19 04:00:49 +0200591 struct eth_device *dev;
592 unsigned short status;
593 unsigned char timer;
594 unsigned int iobase;
595 int card_number = 0;
596 pci_dev_t devbusfn;
597 unsigned int cfrv;
598 int idx = 0;
Marek Vasutb46c7a02020-04-19 03:11:06 +0200599
Marek Vasut5e2ad052020-04-19 04:00:49 +0200600 while (1) {
601 devbusfn = pci_find_devices(supported, idx++);
602 if (devbusfn == -1)
603 break;
wdenkc6097192002-11-03 00:24:07 +0000604
Marek Vasut5e2ad052020-04-19 04:00:49 +0200605 /* Get the chip configuration revision register. */
606 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
wdenkc6097192002-11-03 00:24:07 +0000607
Marek Vasut5e2ad052020-04-19 04:00:49 +0200608 if ((cfrv & CFRV_RN) < DC2114x_BRK) {
609 printf("Error: The chip is not DC21143.\n");
610 continue;
611 }
Marek Vasutb46c7a02020-04-19 03:11:06 +0200612
Marek Vasut5e2ad052020-04-19 04:00:49 +0200613 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
614 status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
615 pci_write_config_word(devbusfn, PCI_COMMAND, status);
wdenkc6097192002-11-03 00:24:07 +0000616
Marek Vasut5e2ad052020-04-19 04:00:49 +0200617 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
618 if (!(status & PCI_COMMAND_MEMORY)) {
619 printf("Error: Can not enable MEMORY access.\n");
620 continue;
621 }
wdenkc6097192002-11-03 00:24:07 +0000622
Marek Vasut5e2ad052020-04-19 04:00:49 +0200623 if (!(status & PCI_COMMAND_MASTER)) {
624 printf("Error: Can not enable Bus Mastering.\n");
625 continue;
626 }
wdenkc6097192002-11-03 00:24:07 +0000627
Marek Vasut5e2ad052020-04-19 04:00:49 +0200628 /* Check the latency timer for values >= 0x60. */
629 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
wdenkc6097192002-11-03 00:24:07 +0000630
Marek Vasut5e2ad052020-04-19 04:00:49 +0200631 if (timer < 0x60) {
632 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
633 0x60);
634 }
wdenkc6097192002-11-03 00:24:07 +0000635
Marek Vasut5e2ad052020-04-19 04:00:49 +0200636 /* read BAR for memory space access */
637 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
638 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
639 debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
wdenkc6097192002-11-03 00:24:07 +0000640
Marek Vasut5e2ad052020-04-19 04:00:49 +0200641 dev = (struct eth_device *)malloc(sizeof(*dev));
642 if (!dev) {
643 printf("Can not allocalte memory of dc21x4x\n");
644 break;
645 }
wdenkc6097192002-11-03 00:24:07 +0000646
Marek Vasut5e2ad052020-04-19 04:00:49 +0200647 memset(dev, 0, sizeof(*dev));
Marek Vasutb46c7a02020-04-19 03:11:06 +0200648
Marek Vasut5e2ad052020-04-19 04:00:49 +0200649 sprintf(dev->name, "dc21x4x#%d", card_number);
wdenkc6097192002-11-03 00:24:07 +0000650
Marek Vasut5e2ad052020-04-19 04:00:49 +0200651 dev->iobase = pci_mem_to_phys(devbusfn, iobase);
652 dev->priv = (void *)devbusfn;
653 dev->init = dc21x4x_init;
654 dev->halt = dc21x4x_halt;
655 dev->send = dc21x4x_send;
656 dev->recv = dc21x4x_recv;
wdenkc6097192002-11-03 00:24:07 +0000657
Marek Vasut5e2ad052020-04-19 04:00:49 +0200658 /* Ensure we're not sleeping. */
659 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
wdenkc6097192002-11-03 00:24:07 +0000660
Marek Vasut5e2ad052020-04-19 04:00:49 +0200661 udelay(10 * 1000);
wdenkc6097192002-11-03 00:24:07 +0000662
Marek Vasut5e2ad052020-04-19 04:00:49 +0200663 read_hw_addr(dev, bis);
wdenkc6097192002-11-03 00:24:07 +0000664
Marek Vasut5e2ad052020-04-19 04:00:49 +0200665 eth_register(dev);
Marek Vasutb46c7a02020-04-19 03:11:06 +0200666
Marek Vasut5e2ad052020-04-19 04:00:49 +0200667 card_number++;
668 }
wdenkc6097192002-11-03 00:24:07 +0000669
Marek Vasut5e2ad052020-04-19 04:00:49 +0200670 return card_number;
wdenkc6097192002-11-03 00:24:07 +0000671}