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git01.mediatek.com / filogic / uboot / 07ba88ef8927f8aab9a48891b499bd63eb24ff7b / . / doc / device-tree-bindings / memory-controllers / st,stm32mp1-ddr.txt
blob: ac6a7df4327d15013b441add9df9ef5c88d52dba [file] [log] [blame]
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]1ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
2
3--------------------
4Required properties:
5--------------------
6- compatible : Should be "st,stm32mp1-ddr"
7- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
8- clocks : controller clocks handle
9- clock-names : associated controller clock names
10 the "ddrphyc" clock is used to check the DDR frequency
11 at phy level according the expected value in "mem-speed" field
12
13the next attributes are DDR parameters, they are generated by DDR tools
14included in STM32 Cube tool
15
16info attributes:
17----------------
18- st,mem-name : name for DDR configuration, simple string for information
Patrick Delaunay29e1a942019-04-10 14:09:23 +0200[diff] [blame]19- st,mem-speed : DDR expected speed for the setting in kHz
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]20- st,mem-size : DDR mem size in byte
21
22
23controlleur attributes:
24-----------------------
25- st,ctl-reg : controleur values depending of the DDR type
26 (DDR3/LPDDR2/LPDDR3)
27 for STM32MP15x: 25 values are requested in this order
28 MSTR
29 MRCTRL0
30 MRCTRL1
31 DERATEEN
32 DERATEINT
33 PWRCTL
34 PWRTMG
35 HWLPCTL
36 RFSHCTL0
37 RFSHCTL3
38 CRCPARCTL0
39 ZQCTL0
40 DFITMG0
41 DFITMG1
42 DFILPCFG0
43 DFIUPD0
44 DFIUPD1
45 DFIUPD2
46 DFIPHYMSTR
47 ODTMAP
48 DBG0
49 DBG1
50 DBGCMD
51 POISONCFG
52 PCCFG
53
54- st,ctl-timing : controleur values depending of frequency and timing parameter
55 of DDR
56 for STM32MP15x: 12 values are requested in this order
57 RFSHTMG
58 DRAMTMG0
59 DRAMTMG1
60 DRAMTMG2
61 DRAMTMG3
62 DRAMTMG4
63 DRAMTMG5
64 DRAMTMG6
65 DRAMTMG7
66 DRAMTMG8
67 DRAMTMG14
68 ODTCFG
69
70- st,ctl-map : controleur values depending of address mapping
71 for STM32MP15x: 9 values are requested in this order
72 ADDRMAP1
73 ADDRMAP2
74 ADDRMAP3
75 ADDRMAP4
76 ADDRMAP5
77 ADDRMAP6
78 ADDRMAP9
79 ADDRMAP10
80 ADDRMAP11
81
82- st,ctl-perf : controleur values depending of performance and scheduling
83 for STM32MP15x: 17 values are requested in this order
84 SCHED
85 SCHED1
86 PERFHPR1
87 PERFLPR1
88 PERFWR1
89 PCFGR_0
90 PCFGW_0
91 PCFGQOS0_0
92 PCFGQOS1_0
93 PCFGWQOS0_0
94 PCFGWQOS1_0
95 PCFGR_1
96 PCFGW_1
97 PCFGQOS0_1
98 PCFGQOS1_1
99 PCFGWQOS0_1
100 PCFGWQOS1_1
101
102phyc attributes:
103----------------
104- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
Patrick Delaunayd892d272019-04-10 14:09:25 +0200[diff] [blame]105 for STM32MP15x: 11 values are requested in this order
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]106 PGCR
107 ACIOCR
108 DXCCR
109 DSGCR
110 DCR
111 ODTCR
112 ZQ0CR1
113 DX0GCR
114 DX1GCR
115 DX2GCR
116 DX3GCR
117
118- st,phy-timing : phy values depending of frequency and timing parameter of DDR
119 for STM32MP15x: 10 values are requested in this order
120 PTR0
121 PTR1
122 PTR2
123 DTPR0
124 DTPR1
125 DTPR2
126 MR0
127 MR1
128 MR2
129 MR3
130
131- st,phy-cal : phy cal depending of calibration or tuning of DDR
Patrick Delaunaya68e2d62020-03-06 11:14:11 +0100[diff] [blame]132 This parameter is optional; when it is absent the built-in PHY
133 calibration is done.
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]134 for STM32MP15x: 12 values are requested in this order
135 DX0DLLCR
136 DX0DQTR
137 DX0DQSTR
138 DX1DLLCR
139 DX1DQTR
140 DX1DQSTR
141 DX2DLLCR
142 DX2DQTR
143 DX2DQSTR
144 DX3DLLCR
145 DX3DQTR
146 DX3DQSTR
147
148Example:
149
150/ {
151 soc {
152 u-boot,dm-spl;
153
154 ddr: ddr@0x5A003000{
155 u-boot,dm-spl;
156 u-boot,dm-pre-reloc;
157
158 compatible = "st,stm32mp1-ddr";
159
160 reg = <0x5A003000 0x550
161 0x5A004000 0x234>;
162
163 clocks = <&rcc_clk AXIDCG>,
164 <&rcc_clk DDRC1>,
165 <&rcc_clk DDRC2>,
166 <&rcc_clk DDRPHYC>,
167 <&rcc_clk DDRCAPB>,
168 <&rcc_clk DDRPHYCAPB>;
169
170 clock-names = "axidcg",
171 "ddrc1",
172 "ddrc2",
173 "ddrphyc",
174 "ddrcapb",
175 "ddrphycapb";
176
177 st,mem-name = "DDR3 2x4Gb 533MHz";
Patrick Delaunay29e1a942019-04-10 14:09:23 +0200[diff] [blame]178 st,mem-speed = <533000>;
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]179 st,mem-size = <0x40000000>;
180
181 st,ctl-reg = <
182 0x00040401 /*MSTR*/
183 0x00000010 /*MRCTRL0*/
184 0x00000000 /*MRCTRL1*/
185 0x00000000 /*DERATEEN*/
186 0x00800000 /*DERATEINT*/
187 0x00000000 /*PWRCTL*/
188 0x00400010 /*PWRTMG*/
189 0x00000000 /*HWLPCTL*/
190 0x00210000 /*RFSHCTL0*/
191 0x00000000 /*RFSHCTL3*/
192 0x00000000 /*CRCPARCTL0*/
193 0xC2000040 /*ZQCTL0*/
194 0x02050105 /*DFITMG0*/
195 0x00000202 /*DFITMG1*/
196 0x07000000 /*DFILPCFG0*/
197 0xC0400003 /*DFIUPD0*/
198 0x00000000 /*DFIUPD1*/
199 0x00000000 /*DFIUPD2*/
200 0x00000000 /*DFIPHYMSTR*/
201 0x00000001 /*ODTMAP*/
202 0x00000000 /*DBG0*/
203 0x00000000 /*DBG1*/
204 0x00000000 /*DBGCMD*/
205 0x00000000 /*POISONCFG*/
206 0x00000010 /*PCCFG*/
207 >;
208
209 st,ctl-timing = <
210 0x0080008A /*RFSHTMG*/
211 0x121B2414 /*DRAMTMG0*/
212 0x000D041B /*DRAMTMG1*/
213 0x0607080E /*DRAMTMG2*/
214 0x0050400C /*DRAMTMG3*/
215 0x07040407 /*DRAMTMG4*/
216 0x06060303 /*DRAMTMG5*/
217 0x02020002 /*DRAMTMG6*/
218 0x00000202 /*DRAMTMG7*/
219 0x00001005 /*DRAMTMG8*/
220 0x000D041B /*DRAMTMG1*/4
221 0x06000600 /*ODTCFG*/
222 >;
223
224 st,ctl-map = <
225 0x00080808 /*ADDRMAP1*/
226 0x00000000 /*ADDRMAP2*/
227 0x00000000 /*ADDRMAP3*/
228 0x00001F1F /*ADDRMAP4*/
229 0x07070707 /*ADDRMAP5*/
230 0x0F070707 /*ADDRMAP6*/
231 0x00000000 /*ADDRMAP9*/
232 0x00000000 /*ADDRMAP10*/
233 0x00000000 /*ADDRMAP11*/
234 >;
235
236 st,ctl-perf = <
237 0x00001201 /*SCHED*/
238 0x00001201 /*SCHED*/1
239 0x01000001 /*PERFHPR1*/
240 0x08000200 /*PERFLPR1*/
241 0x08000400 /*PERFWR1*/
242 0x00010000 /*PCFGR_0*/
243 0x00000000 /*PCFGW_0*/
244 0x02100B03 /*PCFGQOS0_0*/
245 0x00800100 /*PCFGQOS1_0*/
246 0x01100B03 /*PCFGWQOS0_0*/
247 0x01000200 /*PCFGWQOS1_0*/
248 0x00010000 /*PCFGR_1*/
249 0x00000000 /*PCFGW_1*/
250 0x02100B03 /*PCFGQOS0_1*/
251 0x00800000 /*PCFGQOS1_1*/
252 0x01100B03 /*PCFGWQOS0_1*/
253 0x01000200 /*PCFGWQOS1_1*/
254 >;
255
256 st,phy-reg = <
257 0x01442E02 /*PGCR*/
258 0x10400812 /*ACIOCR*/
259 0x00000C40 /*DXCCR*/
260 0xF200001F /*DSGCR*/
261 0x0000000B /*DCR*/
262 0x00010000 /*ODTCR*/
263 0x0000007B /*ZQ0CR1*/
264 0x0000CE81 /*DX0GCR*/
265 0x0000CE81 /*DX1GCR*/
266 0x0000CE81 /*DX2GCR*/
267 0x0000CE81 /*DX3GCR*/
268 >;
269
270 st,phy-timing = <
271 0x0022A41B /*PTR0*/
272 0x047C0740 /*PTR1*/
273 0x042D9C80 /*PTR2*/
274 0x369477D0 /*DTPR0*/
275 0x098A00D8 /*DTPR1*/
276 0x10023600 /*DTPR2*/
277 0x00000830 /*MR0*/
278 0x00000000 /*MR1*/
279 0x00000208 /*MR2*/
280 0x00000000 /*MR3*/
281 >;
282
283 st,phy-cal = <
284 0x40000000 /*DX0DLLCR*/
285 0xFFFFFFFF /*DX0DQTR*/
286 0x3DB02000 /*DX0DQSTR*/
287 0x40000000 /*DX1DLLCR*/
288 0xFFFFFFFF /*DX1DQTR*/
289 0x3DB02000 /*DX1DQSTR*/
290 0x40000000 /*DX2DLLCR*/
291 0xFFFFFFFF /*DX2DQTR*/
292 0x3DB02000 /*DX2DQSTR*/
293 0x40000000 /*DX3DLLCR*/
294 0xFFFFFFFF /*DX3DQTR*/
295 0x3DB02000 /*DX3DQSTR*/
296 >;
297
298 status = "okay";
299 };
300 };
301};