Blame - drivers/reset/Kconfig - filogic/uboot

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Stephen Warren	185ad87	2016-06-17 09:43:58 -0600	[diff] [blame]	1	menu "Reset Controller Support"
				2
				3	config DM_RESET
				4	bool "Enable reset controllers using Driver Model"
				5	depends on DM && OF_CONTROL
				6	help
				7	Enable support for the reset controller driver class. Many hardware
				8	modules are equipped with a reset signal, typically driven by some
				9	reset controller hardware module within the chip. In U-Boot, reset
				10	controller drivers allow control over these reset signals. In some
				11	cases this API is applicable to chips outside the CPU as well,
				12	although driving such reset isgnals using GPIOs may be more
				13	appropriate in this case.
				14
Stephen Warren	6488e64	2016-06-17 09:43:59 -0600	[diff] [blame]	15	config SANDBOX_RESET
				16	bool "Enable the sandbox reset test driver"
				17	depends on DM_MAILBOX && SANDBOX
				18	help
				19	Enable support for a test reset controller implementation, which
				20	simply accepts requests to reset various HW modules without actually
				21	doing anything beyond a little error checking.
				22
Patrice Chotard	1235aa0	2017-03-22 10:54:03 +0100	[diff] [blame]	23	config STI_RESET
				24	bool "Enable the STi reset"
				25	depends on ARCH_STI
				26	help
				27	Support for reset controllers on STMicroelectronics STiH407 family SoCs.
				28	Say Y if you want to control reset signals provided by system config
				29	block.
				30
Patrice Chotard	5c121e1	2017-09-13 18:00:07 +0200	[diff] [blame]	31	config STM32_RESET
				32	bool "Enable the STM32 reset"
Trevor Woerner	2bcc1ed	2020-05-06 08:02:42 -0400	[diff] [blame]	33	depends on ARCH_STM32 \|\| ARCH_STM32MP
Patrice Chotard	5c121e1	2017-09-13 18:00:07 +0200	[diff] [blame]	34	help
				35	Support for reset controllers on STMicroelectronics STM32 family SoCs.
Trevor Woerner	e3d9c99	2020-05-06 08:02:43 -0400	[diff] [blame]	36	This reset driver is compatible with STM32 F4/F7 and H7 SoCs.
Patrice Chotard	5c121e1	2017-09-13 18:00:07 +0200	[diff] [blame]	37
Stephen Warren	3017ab5	2016-09-13 10:45:58 -0600	[diff] [blame]	38	config TEGRA_CAR_RESET
				39	bool "Enable Tegra CAR-based reset driver"
				40	depends on TEGRA_CAR
				41	help
				42	Enable support for manipulating Tegra's on-SoC reset signals via
				43	direct register access to the Tegra CAR (Clock And Reset controller).
				44
Stephen Warren	fccc9c5	2016-08-08 11:28:25 -0600	[diff] [blame]	45	config TEGRA186_RESET
				46	bool "Enable Tegra186 BPMP-based reset driver"
				47	depends on TEGRA186_BPMP
				48	help
				49	Enable support for manipulating Tegra's on-SoC reset signals via IPC
				50	requests to the BPMP (Boot and Power Management Processor).
				51
Andreas Dannenberg	4cfdf4d	2018-08-27 15:57:41 +0530	[diff] [blame]	52	config RESET_TI_SCI
				53	bool "TI System Control Interface (TI SCI) reset driver"
				54	depends on DM_RESET && TI_SCI_PROTOCOL
				55	help
				56	This enables the reset driver support over TI System Control Interface
				57	available on some new TI's SoCs. If you wish to use reset resources
				58	managed by the TI System Controller, say Y here. Otherwise, say N.
				59
Álvaro Fernández Rojas	5161bd3	2017-05-03 15:10:21 +0200	[diff] [blame]	60	config RESET_BCM6345
				61	bool "Reset controller driver for BCM6345"
				62	depends on DM_RESET && ARCH_BMIPS
				63	help
				64	Support reset controller on BCM6345.
				65
Masahiro Yamada	2aa4b5b	2016-10-08 13:25:31 +0900	[diff] [blame]	66	config RESET_UNIPHIER
				67	bool "Reset controller driver for UniPhier SoCs"
				68	depends on ARCH_UNIPHIER
				69	default y
				70	help
				71	Support for reset controllers on UniPhier SoCs.
				72	Say Y if you want to control reset signals provided by System Control
				73	block, Media I/O block, Peripheral Block.
				74
maxims@google.com	750875c	2017-04-17 12:00:24 -0700	[diff] [blame]	75	config AST2500_RESET
				76	bool "Reset controller driver for AST2500 SoCs"
				77	depends on DM_RESET && WDT_ASPEED
				78	default y if ASPEED_AST2500
				79	help
				80	Support for reset controller on AST2500 SoC. This controller uses
				81	watchdog to reset different peripherals and thus only supports
				82	resets that are supported by watchdog. The main limitation though
				83	is that some reset signals, like I2C or MISC reset multiple devices.
				84
Elaine Zhang	6e9a3a7	2017-12-19 18:22:37 +0800	[diff] [blame]	85	config RESET_ROCKCHIP
				86	bool "Reset controller driver for Rockchip SoCs"
				87	depends on DM_RESET && ARCH_ROCKCHIP && CLK
				88	default y
				89	help
				90	Support for reset controller on rockchip SoC. The main limitation
				91	though is that some reset signals, like I2C or MISC reset multiple
				92	devices.
				93
Eugeniy Paltsev	062da42	2019-10-08 19:29:30 +0300	[diff] [blame]	94	config RESET_HSDK
				95	bool "Synopsys HSDK Reset Driver"
				96	depends on DM_RESET && TARGET_HSDK
				97	default y
				98	help
				99	This enables the reset controller driver for HSDK board.
				100
Neil Armstrong	4f03d6b	2018-03-29 14:55:25 +0200	[diff] [blame]	101	config RESET_MESON
				102	bool "Reset controller driver for Amlogic Meson SoCs"
				103	depends on DM_RESET && ARCH_MESON
				104	imply REGMAP
				105	default y
				106	help
				107	Support for reset controller on Amlogic Meson SoC.
				108
Dinh Nguyen	5427f5a	2018-04-04 17:18:20 -0500	[diff] [blame]	109	config RESET_SOCFPGA
				110	bool "Reset controller driver for SoCFPGA"
				111	depends on DM_RESET && ARCH_SOCFPGA
				112	default y
				113	help
				114	Support for reset controller on SoCFPGA platform.
				115
developer	d48dd9a	2018-12-20 16:12:51 +0800	[diff] [blame]	116	config RESET_MEDIATEK
				117	bool "Reset controller driver for MediaTek SoCs"
				118	depends on DM_RESET && ARCH_MEDIATEK && CLK
				119	default y
				120	help
				121	Support for reset controller on MediaTek SoCs.
				122
developer	074393a	2019-09-25 17:45:29 +0800	[diff] [blame]	123	config RESET_MTMIPS
				124	bool "Reset controller driver for MediaTek MIPS platform"
				125	depends on DM_RESET && ARCH_MTMIPS
				126	default y
				127	help
				128	Support for reset controller on MediaTek MIPS platform.
				129
Jagan Teki	7f6c2a8	2019-01-18 22:18:13 +0530	[diff] [blame]	130	config RESET_SUNXI
				131	bool "RESET support for Allwinner SoCs"
				132	depends on DM_RESET && ARCH_SUNXI
				133	default y
				134	help
				135	This enables support for common reset driver for
				136	Allwinner SoCs.
				137
Shawn Guo	8aa8f30	2019-03-20 15:32:39 +0800	[diff] [blame]	138	config RESET_HISILICON
				139	bool "Reset controller driver for HiSilicon SoCs"
				140	depends on DM_RESET
				141	help
				142	Support for reset controller on HiSilicon SoCs.
				143
Patrick Wildt	dbc644f	2019-10-03 16:08:35 +0200	[diff] [blame]	144	config RESET_IMX7
				145	bool "i.MX7/8 Reset Driver"
				146	depends on DM_RESET && (ARCH_MX7 \|\| ARCH_IMX8M)
				147	default y
				148	help
				149	Support for reset controller on i.MX7/8 SoCs.
				150
Sean Anderson	0c1f6bf	2020-06-24 06:41:14 -0400	[diff] [blame]	151	config RESET_SYSCON
				152	bool "Enable generic syscon reset driver support"
				153	depends on DM_RESET
				154	help
				155	Support generic syscon mapped register reset devices.
Nicolas Saenz Julienne	057bbbd	2020-06-29 18:37:23 +0200	[diff] [blame]	156
				157	config RESET_RASPBERRYPI
				158	bool "Raspberry Pi 4 Firmware Reset Controller Driver"
				159	depends on DM_RESET && ARCH_BCM283X
				160	default USB_XHCI_PCI
				161	help
				162	Raspberry Pi 4's co-processor controls some of the board's HW
				163	initialization process, but it's up to Linux to trigger it when
				164	relevant. This driver provides a reset controller capable of
				165	interfacing with RPi4's co-processor and model these firmware
				166	initialization routines as reset lines.
Stephen Warren	185ad87	2016-06-17 09:43:58 -0600	[diff] [blame]	167	endmenu