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git01.mediatek.com / filogic / uboot / 06c91f0513cf758610971f8285600c336a13ed91 / . / drivers / clk / sunxi / clk_h616.c
blob: af97d3bb9f742f303b81de6201538540a5400e37 [file] [log] [blame]
Jernej Skrabece52dc3e2021-01-11 21:11:52 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@siol.net>
4 */
5
6#include <common.h>
7#include <clk-uclass.h>
8#include <dm.h>
9#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -0500[diff] [blame]10#include <clk/sunxi.h>
Jernej Skrabece52dc3e2021-01-11 21:11:52 +0100[diff] [blame]11#include <dt-bindings/clock/sun50i-h616-ccu.h>
12#include <dt-bindings/reset/sun50i-h616-ccu.h>
13#include <linux/bitops.h>
14
15static struct ccu_clk_gate h616_gates[] = {
16 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
17 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
18 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
19
20 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
21 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
22 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
23 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
24 [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
25 [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
26
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]27 [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
28 [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
29 [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
30 [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
31 [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)),
32
Jernej Skrabece52dc3e2021-01-11 21:11:52 +0100[diff] [blame]33 [CLK_SPI0] = GATE(0x940, BIT(31)),
34 [CLK_SPI1] = GATE(0x944, BIT(31)),
35
36 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
37 [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
38
39 [CLK_BUS_EMAC0] = GATE(0x97c, BIT(0)),
40 [CLK_BUS_EMAC1] = GATE(0x97c, BIT(1)),
41
42 [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
43 [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
44
45 [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
46 [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
47
48 [CLK_USB_PHY2] = GATE(0xa78, BIT(29)),
49 [CLK_USB_OHCI2] = GATE(0xa78, BIT(31)),
50
51 [CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
52 [CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
53
54 [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
55 [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
56 [CLK_BUS_OHCI2] = GATE(0xa8c, BIT(2)),
57 [CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
58 [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
59 [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
60 [CLK_BUS_EHCI2] = GATE(0xa8c, BIT(6)),
61 [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
62 [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
63};
64
65static struct ccu_reset h616_resets[] = {
66 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
67 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
68 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
69
70 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
71 [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
72 [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
73 [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
74 [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
75 [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
76
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]77 [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
78 [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
79 [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
80 [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
81 [RST_BUS_I2C4] = RESET(0x91c, BIT(20)),
82
Jernej Skrabece52dc3e2021-01-11 21:11:52 +0100[diff] [blame]83 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
84 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
85
86 [RST_BUS_EMAC0] = RESET(0x97c, BIT(16)),
87 [RST_BUS_EMAC1] = RESET(0x97c, BIT(17)),
88
89 [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
90
91 [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
92
93 [RST_USB_PHY2] = RESET(0xa78, BIT(30)),
94
95 [RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
96
97 [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
98 [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
99 [RST_BUS_OHCI2] = RESET(0xa8c, BIT(18)),
100 [RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
101 [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
102 [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
103 [RST_BUS_EHCI2] = RESET(0xa8c, BIT(22)),
104 [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
105 [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
106};
107
108static const struct ccu_desc h616_ccu_desc = {
109 .gates = h616_gates,
110 .resets = h616_resets,
111};
112
113static int h616_clk_bind(struct udevice *dev)
114{
115 return sunxi_reset_bind(dev, ARRAY_SIZE(h616_resets));
116}
117
118static const struct udevice_id h616_ccu_ids[] = {
119 { .compatible = "allwinner,sun50i-h616-ccu",
120 .data = (ulong)&h616_ccu_desc },
121 { }
122};
123
124U_BOOT_DRIVER(clk_sun50i_h616) = {
125 .name = "sun50i_h616_ccu",
126 .id = UCLASS_CLK,
127 .of_match = h616_ccu_ids,
128 .priv_auto = sizeof(struct ccu_priv),
129 .ops = &sunxi_clk_ops,
130 .probe = sunxi_clk_probe,
131 .bind = h616_clk_bind,
132};