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git01.mediatek.com / filogic / uboot / 05725edf751242b2d7bf95643eb9c699be7d1502 / . / arch / arm / dts / k2e.dtsi
blob: 675fb8e492c6aa0478a6d5df01b30fbe1e281b7d [file] [log] [blame]
Lokesh Vutla2c14c642015-09-19 15:00:22 +0530[diff] [blame]1/*
2 * Copyright 2013-2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Edison soc device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/ {
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 interrupt-parent = <&gic>;
17
18 cpu@0 {
19 compatible = "arm,cortex-a15";
20 device_type = "cpu";
21 reg = <0>;
22 };
23
24 cpu@1 {
25 compatible = "arm,cortex-a15";
26 device_type = "cpu";
27 reg = <1>;
28 };
29
30 cpu@2 {
31 compatible = "arm,cortex-a15";
32 device_type = "cpu";
33 reg = <2>;
34 };
35
36 cpu@3 {
37 compatible = "arm,cortex-a15";
38 device_type = "cpu";
39 reg = <3>;
40 };
41 };
42
43 soc {
44 /include/ "k2e-clocks.dtsi"
45
46 usb: usb@2680000 {
47 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
48 dwc3@2690000 {
49 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
50 };
51 };
52
53 usb1_phy: usb_phy@2620750 {
54 compatible = "ti,keystone-usbphy";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 reg = <0x2620750 24>;
58 status = "disabled";
59 };
60
61 usb1: usb@25000000 {
62 compatible = "ti,keystone-dwc3";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x25000000 0x10000>;
66 clocks = <&clkusb1>;
67 clock-names = "usb";
68 interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
69 ranges;
70 dma-coherent;
71 dma-ranges;
72 status = "disabled";
73
74 dwc3@25010000 {
75 compatible = "synopsys,dwc3";
76 reg = <0x25010000 0x70000>;
77 interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
78 usb-phy = <&usb1_phy>, <&usb1_phy>;
79 };
80 };
81
82 dspgpio0: keystone_dsp_gpio@02620240 {
83 compatible = "ti,keystone-dsp-gpio";
84 gpio-controller;
85 #gpio-cells = <2>;
86 gpio,syscon-dev = <&devctrl 0x240>;
87 };
88
89 pcie1: pcie@21020000 {
90 compatible = "ti,keystone-pcie","snps,dw-pcie";
91 clocks = <&clkpcie1>;
92 clock-names = "pcie";
93 #address-cells = <3>;
94 #size-cells = <2>;
95 reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
96 ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
97 0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
98
99 status = "disabled";
100 device_type = "pci";
101 num-lanes = <2>;
102
103 #interrupt-cells = <1>;
104 interrupt-map-mask = <0 0 0 7>;
105 interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
106 <0 0 0 2 &pcie_intc1 1>, /* INT B */
107 <0 0 0 3 &pcie_intc1 2>, /* INT C */
108 <0 0 0 4 &pcie_intc1 3>; /* INT D */
109
110 pcie_msi_intc1: msi-interrupt-controller {
111 interrupt-controller;
112 #interrupt-cells = <1>;
113 interrupt-parent = <&gic>;
114 interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
115 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
116 <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
117 <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
118 <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
119 <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
120 <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
121 <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
122 };
123
124 pcie_intc1: legacy-interrupt-controller {
125 interrupt-controller;
126 #interrupt-cells = <1>;
127 interrupt-parent = <&gic>;
128 interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
129 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
130 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
131 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
132 };
133 };
134
135 mdio: mdio@24200f00 {
136 compatible = "ti,keystone_mdio", "ti,davinci_mdio";
137 #address-cells = <1>;
138 #size-cells = <0>;
139 reg = <0x24200f00 0x100>;
140 status = "disabled";
141 clocks = <&clkcpgmac>;
142 clock-names = "fck";
143 bus_freq = <2500000>;
144 };
145 /include/ "k2e-netcp.dtsi"
146 };
147};